mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 23:35:26 +07:00
12e5155783
Add PSCI node for r8a7795 SoC, and cpu node enable-method property is set to "psci". Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
734 lines
20 KiB
Plaintext
734 lines
20 KiB
Plaintext
/*
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* Device Tree Source for the r8a7795 SoC
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*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "renesas,r8a7795";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* 1 core only at this point */
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a57_0: cpu@0 {
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x0>;
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device_type = "cpu";
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enable-method = "psci";
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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/*
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* The external audio clocks are configured as 0 Hz fixed frequency
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* clocks by default.
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* Boards that provide audio clocks should override them.
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*/
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audio_clk_a: audio_clk_a {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_b: audio_clk_b {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_c: audio_clk_c {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@0xf1010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xf1010000 0 0x1000>,
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<0x0 0xf1020000 0 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 16>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 912>;
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power-domains = <&cpg>;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 28>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 911>;
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power-domains = <&cpg>;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 15>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 910>;
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power-domains = <&cpg>;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 16>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 909>;
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power-domains = <&cpg>;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 18>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 908>;
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power-domains = <&cpg>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 26>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 907>;
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power-domains = <&cpg>;
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};
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gpio6: gpio@e6055400 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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reg = <0 0xe6055400 0 0x50>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 906>;
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power-domains = <&cpg>;
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};
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gpio7: gpio@e6055800 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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reg = <0 0xe6055800 0 0x50>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 224 4>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 905>;
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power-domains = <&cpg>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7795-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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};
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audma0: dma-controller@ec700000 {
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compatible = "renesas,rcar-dmac";
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reg = <0 0xec700000 0 0x10000>;
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interrupts = <0 350 IRQ_TYPE_LEVEL_HIGH
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0 320 IRQ_TYPE_LEVEL_HIGH
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0 321 IRQ_TYPE_LEVEL_HIGH
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0 322 IRQ_TYPE_LEVEL_HIGH
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0 323 IRQ_TYPE_LEVEL_HIGH
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0 324 IRQ_TYPE_LEVEL_HIGH
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0 325 IRQ_TYPE_LEVEL_HIGH
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0 326 IRQ_TYPE_LEVEL_HIGH
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0 327 IRQ_TYPE_LEVEL_HIGH
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0 328 IRQ_TYPE_LEVEL_HIGH
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0 329 IRQ_TYPE_LEVEL_HIGH
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0 330 IRQ_TYPE_LEVEL_HIGH
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0 331 IRQ_TYPE_LEVEL_HIGH
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0 332 IRQ_TYPE_LEVEL_HIGH
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0 333 IRQ_TYPE_LEVEL_HIGH
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0 334 IRQ_TYPE_LEVEL_HIGH
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0 335 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15";
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clocks = <&cpg CPG_MOD 502>;
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clock-names = "fck";
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power-domains = <&cpg>;
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#dma-cells = <1>;
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dma-channels = <16>;
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};
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audma1: dma-controller@ec720000 {
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compatible = "renesas,rcar-dmac";
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reg = <0 0xec720000 0 0x10000>;
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interrupts = <0 351 IRQ_TYPE_LEVEL_HIGH
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0 336 IRQ_TYPE_LEVEL_HIGH
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0 337 IRQ_TYPE_LEVEL_HIGH
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0 338 IRQ_TYPE_LEVEL_HIGH
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0 339 IRQ_TYPE_LEVEL_HIGH
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0 340 IRQ_TYPE_LEVEL_HIGH
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0 341 IRQ_TYPE_LEVEL_HIGH
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0 342 IRQ_TYPE_LEVEL_HIGH
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0 343 IRQ_TYPE_LEVEL_HIGH
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0 344 IRQ_TYPE_LEVEL_HIGH
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0 345 IRQ_TYPE_LEVEL_HIGH
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0 346 IRQ_TYPE_LEVEL_HIGH
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0 347 IRQ_TYPE_LEVEL_HIGH
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0 348 IRQ_TYPE_LEVEL_HIGH
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0 349 IRQ_TYPE_LEVEL_HIGH
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0 382 IRQ_TYPE_LEVEL_HIGH
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0 383 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15";
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clocks = <&cpg CPG_MOD 501>;
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clock-names = "fck";
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power-domains = <&cpg>;
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#dma-cells = <1>;
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dma-channels = <16>;
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};
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pfc: pfc@e6060000 {
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compatible = "renesas,pfc-r8a7795";
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reg = <0 0xe6060000 0 0x50c>;
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};
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dmac0: dma-controller@e6700000 {
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/* Empty node for now */
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};
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dmac1: dma-controller@e7300000 {
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/* Empty node for now */
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};
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dmac2: dma-controller@e7310000 {
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/* Empty node for now */
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};
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avb: ethernet@e6800000 {
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compatible = "renesas,etheravb-r8a7795";
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reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15",
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"ch16", "ch17", "ch18", "ch19",
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"ch20", "ch21", "ch22", "ch23",
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"ch24";
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clocks = <&cpg CPG_MOD 812>;
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power-domains = <&cpg>;
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phy-mode = "rgmii-id";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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hscif0: serial@e6540000 {
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compatible = "renesas,hscif-r8a7795", "renesas,hscif";
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reg = <0 0xe6540000 0 96>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 520>;
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clock-names = "sci_ick";
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dmas = <&dmac1 0x31>, <&dmac1 0x30>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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status = "disabled";
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};
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hscif1: serial@e6550000 {
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compatible = "renesas,hscif-r8a7795", "renesas,hscif";
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reg = <0 0xe6550000 0 96>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 519>;
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clock-names = "sci_ick";
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dmas = <&dmac1 0x33>, <&dmac1 0x32>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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status = "disabled";
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};
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hscif2: serial@e6560000 {
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compatible = "renesas,hscif-r8a7795", "renesas,hscif";
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reg = <0 0xe6560000 0 96>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 518>;
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clock-names = "sci_ick";
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dmas = <&dmac1 0x35>, <&dmac1 0x34>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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status = "disabled";
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};
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hscif3: serial@e66a0000 {
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compatible = "renesas,hscif-r8a7795", "renesas,hscif";
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reg = <0 0xe66a0000 0 96>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 517>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x37>, <&dmac0 0x36>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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status = "disabled";
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};
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hscif4: serial@e66b0000 {
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compatible = "renesas,hscif-r8a7795", "renesas,hscif";
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reg = <0 0xe66b0000 0 96>;
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 516>;
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clock-names = "sci_ick";
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dmas = <&dmac0 0x39>, <&dmac0 0x38>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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status = "disabled";
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};
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a7795", "renesas,scif";
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reg = <0 0xe6e60000 0 64>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 207>;
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clock-names = "sci_ick";
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dmas = <&dmac1 0x51>, <&dmac1 0x50>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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status = "disabled";
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};
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scif1: serial@e6e68000 {
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compatible = "renesas,scif-r8a7795", "renesas,scif";
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reg = <0 0xe6e68000 0 64>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 206>;
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clock-names = "sci_ick";
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dmas = <&dmac1 0x53>, <&dmac1 0x52>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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status = "disabled";
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};
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scif2: serial@e6e88000 {
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compatible = "renesas,scif-r8a7795", "renesas,scif";
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reg = <0 0xe6e88000 0 64>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 310>;
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clock-names = "sci_ick";
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dmas = <&dmac1 0x13>, <&dmac1 0x12>;
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dma-names = "tx", "rx";
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@e6c50000 {
|
|
compatible = "renesas,scif-r8a7795", "renesas,scif";
|
|
reg = <0 0xe6c50000 0 64>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 204>;
|
|
clock-names = "sci_ick";
|
|
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif4: serial@e6c40000 {
|
|
compatible = "renesas,scif-r8a7795", "renesas,scif";
|
|
reg = <0 0xe6c40000 0 64>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 203>;
|
|
clock-names = "sci_ick";
|
|
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif5: serial@e6f30000 {
|
|
compatible = "renesas,scif-r8a7795", "renesas,scif";
|
|
reg = <0 0xe6f30000 0 64>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 202>;
|
|
clock-names = "sci_ick";
|
|
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@e6500000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a7795";
|
|
reg = <0 0xe6500000 0 0x40>;
|
|
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 931>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@e6508000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a7795";
|
|
reg = <0 0xe6508000 0 0x40>;
|
|
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 930>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@e6510000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a7795";
|
|
reg = <0 0xe6510000 0 0x40>;
|
|
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 929>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@e66d0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a7795";
|
|
reg = <0 0xe66d0000 0 0x40>;
|
|
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 928>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@e66d8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a7795";
|
|
reg = <0 0xe66d8000 0 0x40>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 927>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@e66e0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a7795";
|
|
reg = <0 0xe66e0000 0 0x40>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 919>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@e66e8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a7795";
|
|
reg = <0 0xe66e8000 0 0x40>;
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 918>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rcar_sound: sound@ec500000 {
|
|
/*
|
|
* #sound-dai-cells is required
|
|
*
|
|
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
|
|
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
|
|
*/
|
|
/*
|
|
* #clock-cells is required for audio_clkout0/1/2/3
|
|
*
|
|
* clkout : #clock-cells = <0>; <&rcar_sound>;
|
|
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
|
|
*/
|
|
compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3";
|
|
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
|
<0 0xec5a0000 0 0x100>, /* ADG */
|
|
<0 0xec540000 0 0x1000>, /* SSIU */
|
|
<0 0xec541000 0 0x280>, /* SSI */
|
|
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
|
|
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
|
|
|
clocks = <&cpg CPG_MOD 1005>,
|
|
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
|
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
|
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
|
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
|
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
|
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
|
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
|
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
|
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
|
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
|
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
|
<&audio_clk_a>, <&audio_clk_b>,
|
|
<&audio_clk_c>,
|
|
<&cpg CPG_CORE R8A7795_CLK_S0D4>;
|
|
clock-names = "ssi-all",
|
|
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
|
|
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
|
|
"ssi.1", "ssi.0",
|
|
"src.9", "src.8", "src.7", "src.6",
|
|
"src.5", "src.4", "src.3", "src.2",
|
|
"src.1", "src.0",
|
|
"dvc.0", "dvc.1",
|
|
"clk_a", "clk_b", "clk_c", "clk_i";
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
|
|
rcar_sound,dvc {
|
|
dvc0: dvc@0 {
|
|
dmas = <&audma0 0xbc>;
|
|
dma-names = "tx";
|
|
};
|
|
dvc1: dvc@1 {
|
|
dmas = <&audma0 0xbe>;
|
|
dma-names = "tx";
|
|
};
|
|
};
|
|
|
|
rcar_sound,src {
|
|
src0: src@0 {
|
|
interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x85>, <&audma1 0x9a>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src1: src@1 {
|
|
interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x87>, <&audma1 0x9c>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src2: src@2 {
|
|
interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x89>, <&audma1 0x9e>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src3: src@3 {
|
|
interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x8b>, <&audma1 0xa0>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src4: src@4 {
|
|
interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x8d>, <&audma1 0xb0>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src5: src@5 {
|
|
interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x8f>, <&audma1 0xb2>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src6: src@6 {
|
|
interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x91>, <&audma1 0xb4>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src7: src@7 {
|
|
interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x93>, <&audma1 0xb6>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src8: src@8 {
|
|
interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x95>, <&audma1 0xb8>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src9: src@9 {
|
|
interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x97>, <&audma1 0xba>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
};
|
|
|
|
rcar_sound,ssi {
|
|
ssi0: ssi@0 {
|
|
interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi1: ssi@1 {
|
|
interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi2: ssi@2 {
|
|
interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi3: ssi@3 {
|
|
interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi4: ssi@4 {
|
|
interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi5: ssi@5 {
|
|
interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi6: ssi@6 {
|
|
interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi7: ssi@7 {
|
|
interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi8: ssi@8 {
|
|
interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi9: ssi@9 {
|
|
interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|