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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 51 franklin st fifth floor boston ma 02110 1301 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 246 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190530000436.674189849@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
65 lines
1.7 KiB
C
65 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* IP block integration code for the HDQ1W/1-wire IP block
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*
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* Copyright (C) 2012 Texas Instruments, Inc.
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* Paul Walmsley
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*
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* Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
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* Avinash.H.M <avinashhm@ti.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include "soc.h"
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#include "omap_hwmod.h"
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#include "omap_device.h"
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#include "hdq1w.h"
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#include "prm.h"
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#include "common.h"
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/**
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* omap_hdq1w_reset - reset the OMAP HDQ1W module
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* @oh: struct omap_hwmod *
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*
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* OCP soft reset the HDQ1W IP block. Section 20.6.1.4 "HDQ1W/1-Wire
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* Software Reset" of the OMAP34xx Technical Reference Manual Revision
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* ZR (SWPU223R) does not include the rather important fact that, for
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* the reset to succeed, the HDQ1W module's internal clock gate must be
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* programmed to allow the clock to propagate to the rest of the
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* module. In this sense, it's rather similar to the I2C custom reset
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* function. Returns 0.
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*/
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int omap_hdq1w_reset(struct omap_hwmod *oh)
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{
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u32 v;
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int c = 0;
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/* Write to the SOFTRESET bit */
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omap_hwmod_softreset(oh);
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/* Enable the module's internal clocks */
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v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);
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v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;
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omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
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/* Poll on RESETDONE bit */
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omap_test_timeout((omap_hwmod_read(oh,
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oh->class->sysc->syss_offs)
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& SYSS_RESETDONE_MASK),
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MAX_MODULE_SOFTRESET_WAIT, c);
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if (c == MAX_MODULE_SOFTRESET_WAIT)
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pr_warn("%s: %s: softreset failed (waited %d usec)\n",
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__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
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else
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pr_debug("%s: %s: softreset in %d usec\n", __func__,
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oh->name, c);
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return 0;
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}
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