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26b754f994
On i.MX51/i.MX53 it is necessary to set the DBGEN bit in ARM_GPC register in order to turn on the debug clocks. The DBGEN bit of ARM_GPC register has the following description in the i.MX53 Reference Manual: "This allows the user to manually activate clocks within the debug system. This register bit directly controls the platform's dbgen_out output signal which connects to the DAP_SYS to enable all debug clocks. Once enabled, the clocks cannot be disabled except by asserting the disable_trace input of the DAP_SYS." Based on a previous patch from Sebastian Reichel. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
165 lines
3.2 KiB
C
165 lines
3.2 KiB
C
/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*
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* This file contains the CPU initialization code.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "hardware.h"
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#include "common.h"
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static int mx5_cpu_rev = -1;
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#define IIM_SREV 0x24
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static u32 imx5_read_srev_reg(const char *compat)
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{
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void __iomem *iim_base;
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struct device_node *np;
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u32 srev;
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np = of_find_compatible_node(NULL, NULL, compat);
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iim_base = of_iomap(np, 0);
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WARN_ON(!iim_base);
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srev = readl(iim_base + IIM_SREV) & 0xff;
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iounmap(iim_base);
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return srev;
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}
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static int get_mx51_srev(void)
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{
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u32 rev = imx5_read_srev_reg("fsl,imx51-iim");
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switch (rev) {
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case 0x0:
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return IMX_CHIP_REVISION_2_0;
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case 0x10:
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return IMX_CHIP_REVISION_3_0;
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default:
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return IMX_CHIP_REVISION_UNKNOWN;
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}
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}
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/*
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* Returns:
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* the silicon revision of the cpu
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*/
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int mx51_revision(void)
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{
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if (mx5_cpu_rev == -1)
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mx5_cpu_rev = get_mx51_srev();
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return mx5_cpu_rev;
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}
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EXPORT_SYMBOL(mx51_revision);
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#ifdef CONFIG_NEON
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/*
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* All versions of the silicon before Rev. 3 have broken NEON implementations.
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* Dependent on link order - so the assumption is that vfp_init is called
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* before us.
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*/
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int __init mx51_neon_fixup(void)
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{
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if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
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(elf_hwcap & HWCAP_NEON)) {
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elf_hwcap &= ~HWCAP_NEON;
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pr_info("Turning off NEON support, detected broken NEON implementation\n");
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}
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return 0;
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}
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#endif
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static int get_mx53_srev(void)
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{
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u32 rev = imx5_read_srev_reg("fsl,imx53-iim");
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switch (rev) {
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case 0x0:
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return IMX_CHIP_REVISION_1_0;
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case 0x2:
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return IMX_CHIP_REVISION_2_0;
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case 0x3:
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return IMX_CHIP_REVISION_2_1;
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default:
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return IMX_CHIP_REVISION_UNKNOWN;
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}
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}
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/*
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* Returns:
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* the silicon revision of the cpu
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*/
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int mx53_revision(void)
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{
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if (mx5_cpu_rev == -1)
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mx5_cpu_rev = get_mx53_srev();
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return mx5_cpu_rev;
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}
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EXPORT_SYMBOL(mx53_revision);
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#define ARM_GPC 0x4
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#define DBGEN BIT(16)
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/*
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* This enables the DBGEN bit in ARM_GPC register, which is
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* required for accessing some performance counter features.
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* Technically it is only required while perf is used, but to
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* keep the source code simple we just enable it all the time
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* when the kernel configuration allows using the feature.
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*/
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void __init imx5_pmu_init(void)
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{
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void __iomem *tigerp_base;
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struct device_node *np;
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u32 gpc;
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if (!IS_ENABLED(CONFIG_ARM_PMU))
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return;
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu");
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if (!np)
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return;
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if (!of_property_read_bool(np, "secure-reg-access"))
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goto exit;
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of_node_put(np);
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np = of_find_compatible_node(NULL, NULL, "fsl,imx51-tigerp");
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if (!np)
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return;
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tigerp_base = of_iomap(np, 0);
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if (!tigerp_base)
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goto exit;
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gpc = readl_relaxed(tigerp_base + ARM_GPC);
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gpc |= DBGEN;
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writel_relaxed(gpc, tigerp_base + ARM_GPC);
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iounmap(tigerp_base);
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exit:
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of_node_put(np);
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}
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