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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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81af63a4af
Move the plane clip rectangle handling into drm_atomic_helper_check_plane_state(). Drivers no longer have to worry about such mundane details. v2: Convert armada, rcar, and sun4i as well v3: Resolve simple_kms_helper conflict Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Brian Starkey <brian.starkey@arm.com> Cc: Mali DP Maintainers <malidp@foss.arm.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Gustavo Padovan <gustavo@padovan.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: CK Hu <ck.hu@mediatek.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Rob Clark <robdclark@gmail.com> Cc: Ben Skeggs <bskeggs@redhat.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Sandy Huang <hjc@rock-chips.com> Cc: "Heiko Stübner" <heiko@sntech.de> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: VMware Graphics <linux-graphics-maintainer@vmware.com> Cc: Sinclair Yeh <syeh@vmware.com> Cc: Thomas Hellstrom <thellstrom@vmware.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Archit Taneja <architt@codeaurora.org> Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: nouveau@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: Russell King <rmk+kernel@armlinux.org.uk> Suggested-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Archit Taneja <architt@codeaurora.org> #msm Link: https://patchwork.freedesktop.org/patch/msgid/20180123170857.13818-5-ville.syrjala@linux.intel.com Acked-by: Liviu Dudau <liviu.dudau@arm.com> #hdlcd,malidp Acked-by: Philipp Zabel <p.zabel@pengutronix.de> #imx,mtk Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> #vmwgfx Acked-by: Neil Armstrong <narmstrong@baylibre.com> #meson Acked-by: Shawn Guo <shawnguo@kernel.org> #zte
345 lines
10 KiB
C
345 lines
10 KiB
C
/*
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* Copyright (C) 2013-2015 ARM Limited
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* Author: Liviu Dudau <Liviu.Dudau@arm.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*
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* Implementation of a CRTC class for the HDLCD driver.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_of.h>
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#include <drm/drm_plane_helper.h>
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#include <linux/clk.h>
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#include <linux/of_graph.h>
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#include <linux/platform_data/simplefb.h>
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#include <video/videomode.h>
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#include "hdlcd_drv.h"
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#include "hdlcd_regs.h"
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/*
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* The HDLCD controller is a dumb RGB streamer that gets connected to
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* a single HDMI transmitter or in the case of the ARM Models it gets
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* emulated by the software that does the actual rendering.
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*
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*/
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static void hdlcd_crtc_cleanup(struct drm_crtc *crtc)
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{
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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/* stop the controller on cleanup */
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hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
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drm_crtc_cleanup(crtc);
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}
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static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc)
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{
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
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hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);
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return 0;
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}
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static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc)
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{
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
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hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
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}
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static const struct drm_crtc_funcs hdlcd_crtc_funcs = {
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.destroy = hdlcd_crtc_cleanup,
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.set_config = drm_atomic_helper_set_config,
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.page_flip = drm_atomic_helper_page_flip,
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.reset = drm_atomic_helper_crtc_reset,
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.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
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.enable_vblank = hdlcd_crtc_enable_vblank,
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.disable_vblank = hdlcd_crtc_disable_vblank,
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};
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static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS;
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/*
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* Setup the HDLCD registers for decoding the pixels out of the framebuffer
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*/
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static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc)
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{
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unsigned int btpp;
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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const struct drm_framebuffer *fb = crtc->primary->state->fb;
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uint32_t pixel_format;
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struct simplefb_format *format = NULL;
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int i;
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pixel_format = fb->format->format;
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for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
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if (supported_formats[i].fourcc == pixel_format)
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format = &supported_formats[i];
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}
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if (WARN_ON(!format))
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return 0;
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/* HDLCD uses 'bytes per pixel', zero means 1 byte */
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btpp = (format->bits_per_pixel + 7) / 8;
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hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);
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/*
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* The format of the HDLCD_REG_<color>_SELECT register is:
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* - bits[23:16] - default value for that color component
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* - bits[11:8] - number of bits to extract for each color component
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* - bits[4:0] - index of the lowest bit to extract
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*
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* The default color value is used when bits[11:8] are zero, when the
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* pixel is outside the visible frame area or when there is a
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* buffer underrun.
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*/
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hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset |
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#ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN
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0x00ff0000 | /* show underruns in red */
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#endif
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((format->red.length & 0xf) << 8));
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hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset |
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((format->green.length & 0xf) << 8));
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hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset |
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((format->blue.length & 0xf) << 8));
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return 0;
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}
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static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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struct drm_display_mode *m = &crtc->state->adjusted_mode;
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struct videomode vm;
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unsigned int polarities, err;
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vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
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vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
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vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
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vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
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vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
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vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
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polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA;
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if (m->flags & DRM_MODE_FLAG_PHSYNC)
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polarities |= HDLCD_POLARITY_HSYNC;
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if (m->flags & DRM_MODE_FLAG_PVSYNC)
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polarities |= HDLCD_POLARITY_VSYNC;
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/* Allow max number of outstanding requests and largest burst size */
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hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
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HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16);
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hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
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hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
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hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
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hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
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hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
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hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
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hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
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hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
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hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);
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err = hdlcd_set_pxl_fmt(crtc);
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if (err)
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return;
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clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);
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}
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static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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clk_prepare_enable(hdlcd->clk);
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hdlcd_crtc_mode_set_nofb(crtc);
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hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
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drm_crtc_vblank_on(crtc);
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}
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static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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drm_crtc_vblank_off(crtc);
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hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
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clk_disable_unprepare(hdlcd->clk);
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}
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static int hdlcd_crtc_atomic_check(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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struct drm_display_mode *mode = &state->adjusted_mode;
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long rate, clk_rate = mode->clock * 1000;
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rate = clk_round_rate(hdlcd->clk, clk_rate);
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if (rate != clk_rate) {
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/* clock required by mode not supported by hardware */
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return -EINVAL;
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}
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return 0;
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}
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static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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struct drm_pending_vblank_event *event = crtc->state->event;
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if (event) {
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crtc->state->event = NULL;
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spin_lock_irq(&crtc->dev->event_lock);
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if (drm_crtc_vblank_get(crtc) == 0)
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drm_crtc_arm_vblank_event(crtc, event);
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else
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drm_crtc_send_vblank_event(crtc, event);
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spin_unlock_irq(&crtc->dev->event_lock);
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}
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}
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static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = {
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.atomic_check = hdlcd_crtc_atomic_check,
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.atomic_begin = hdlcd_crtc_atomic_begin,
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.atomic_enable = hdlcd_crtc_atomic_enable,
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.atomic_disable = hdlcd_crtc_atomic_disable,
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};
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static int hdlcd_plane_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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struct drm_crtc_state *crtc_state;
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u32 src_h = state->src_h >> 16;
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/* only the HDLCD_REG_FB_LINE_COUNT register has a limit */
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if (src_h >= HDLCD_MAX_YRES) {
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DRM_DEBUG_KMS("Invalid source width: %d\n", src_h);
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return -EINVAL;
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}
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if (!state->fb || !state->crtc)
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return 0;
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crtc_state = drm_atomic_get_existing_crtc_state(state->state,
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state->crtc);
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if (!crtc_state) {
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DRM_DEBUG_KMS("Invalid crtc state\n");
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return -EINVAL;
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}
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return drm_atomic_helper_check_plane_state(state, crtc_state,
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DRM_PLANE_HELPER_NO_SCALING,
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DRM_PLANE_HELPER_NO_SCALING,
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false, true);
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}
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static void hdlcd_plane_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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struct drm_framebuffer *fb = plane->state->fb;
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struct hdlcd_drm_private *hdlcd;
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u32 dest_h;
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dma_addr_t scanout_start;
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if (!fb)
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return;
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dest_h = drm_rect_height(&plane->state->dst);
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scanout_start = drm_fb_cma_get_gem_addr(fb, plane->state, 0);
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hdlcd = plane->dev->dev_private;
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hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);
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hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]);
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hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
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hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
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}
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static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = {
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.atomic_check = hdlcd_plane_atomic_check,
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.atomic_update = hdlcd_plane_atomic_update,
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};
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static void hdlcd_plane_destroy(struct drm_plane *plane)
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{
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drm_plane_helper_disable(plane);
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drm_plane_cleanup(plane);
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}
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static const struct drm_plane_funcs hdlcd_plane_funcs = {
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.update_plane = drm_atomic_helper_update_plane,
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.disable_plane = drm_atomic_helper_disable_plane,
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.destroy = hdlcd_plane_destroy,
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.reset = drm_atomic_helper_plane_reset,
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.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
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};
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static struct drm_plane *hdlcd_plane_init(struct drm_device *drm)
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{
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struct hdlcd_drm_private *hdlcd = drm->dev_private;
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struct drm_plane *plane = NULL;
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u32 formats[ARRAY_SIZE(supported_formats)], i;
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int ret;
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plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
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if (!plane)
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return ERR_PTR(-ENOMEM);
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for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
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formats[i] = supported_formats[i].fourcc;
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ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs,
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formats, ARRAY_SIZE(formats),
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NULL,
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DRM_PLANE_TYPE_PRIMARY, NULL);
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if (ret)
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return ERR_PTR(ret);
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drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs);
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hdlcd->plane = plane;
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return plane;
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}
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int hdlcd_setup_crtc(struct drm_device *drm)
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{
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struct hdlcd_drm_private *hdlcd = drm->dev_private;
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struct drm_plane *primary;
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int ret;
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primary = hdlcd_plane_init(drm);
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if (IS_ERR(primary))
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return PTR_ERR(primary);
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ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL,
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&hdlcd_crtc_funcs, NULL);
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if (ret) {
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hdlcd_plane_destroy(primary);
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return ret;
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}
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drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs);
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return 0;
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}
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