mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 20:15:30 +07:00
8df728e1ae
The cmpxchg implementation introduced by commit c342f78217 ("arm64:
cmpxchg: patch in lse instructions when supported by the CPU") performs
an apparently redundant register move of [old] to [oldval] in the
success case - it always uses the same register width as [oldval] was
originally loaded with, and is only executed when [old] and [oldval] are
known to be equal anyway.
The only effect it seemingly does have is to take up a surprising amount
of space in the kernel text, as removing it reveals:
text data bss dec hex filename
12426658 1348614 4499749 18275021 116dacd vmlinux.o.new
12429238 1348614 4499749 18277601 116e4e1 vmlinux.o.old
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
331 lines
10 KiB
C
331 lines
10 KiB
C
/*
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* Based on arch/arm/include/asm/atomic.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2002 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ATOMIC_LL_SC_H
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#define __ASM_ATOMIC_LL_SC_H
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#ifndef __ARM64_IN_ATOMIC_IMPL
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#error "please don't include this file directly"
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#endif
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/*
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* AArch64 UP and SMP safe atomic ops. We use load exclusive and
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* store exclusive to ensure that these are atomic. We may loop
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* to ensure that the update happens.
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*
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* NOTE: these functions do *not* follow the PCS and must explicitly
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* save any clobbered registers other than x0 (regardless of return
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* value). This is achieved through -fcall-saved-* compiler flags for
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* this file, which unfortunately don't work on a per-function basis
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* (the optimize attribute silently ignores these options).
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*/
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#define ATOMIC_OP(op, asm_op) \
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__LL_SC_INLINE void \
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__LL_SC_PREFIX(atomic_##op(int i, atomic_t *v)) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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asm volatile("// atomic_" #op "\n" \
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" prfm pstl1strm, %2\n" \
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"1: ldxr %w0, %2\n" \
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" " #asm_op " %w0, %w0, %w3\n" \
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" stxr %w1, %w0, %2\n" \
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" cbnz %w1, 1b" \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i)); \
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} \
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__LL_SC_EXPORT(atomic_##op);
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#define ATOMIC_OP_RETURN(name, mb, acq, rel, cl, op, asm_op) \
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__LL_SC_INLINE int \
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__LL_SC_PREFIX(atomic_##op##_return##name(int i, atomic_t *v)) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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asm volatile("// atomic_" #op "_return" #name "\n" \
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" prfm pstl1strm, %2\n" \
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"1: ld" #acq "xr %w0, %2\n" \
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" " #asm_op " %w0, %w0, %w3\n" \
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" st" #rel "xr %w1, %w0, %2\n" \
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" cbnz %w1, 1b\n" \
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" " #mb \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i) \
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: cl); \
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\
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return result; \
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} \
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__LL_SC_EXPORT(atomic_##op##_return##name);
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#define ATOMIC_FETCH_OP(name, mb, acq, rel, cl, op, asm_op) \
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__LL_SC_INLINE int \
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__LL_SC_PREFIX(atomic_fetch_##op##name(int i, atomic_t *v)) \
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{ \
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unsigned long tmp; \
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int val, result; \
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\
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asm volatile("// atomic_fetch_" #op #name "\n" \
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" prfm pstl1strm, %3\n" \
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"1: ld" #acq "xr %w0, %3\n" \
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" " #asm_op " %w1, %w0, %w4\n" \
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" st" #rel "xr %w2, %w1, %3\n" \
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" cbnz %w2, 1b\n" \
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" " #mb \
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: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i) \
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: cl); \
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\
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return result; \
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} \
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__LL_SC_EXPORT(atomic_fetch_##op##name);
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#define ATOMIC_OPS(...) \
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ATOMIC_OP(__VA_ARGS__) \
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ATOMIC_OP_RETURN( , dmb ish, , l, "memory", __VA_ARGS__)\
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ATOMIC_OP_RETURN(_relaxed, , , , , __VA_ARGS__)\
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ATOMIC_OP_RETURN(_acquire, , a, , "memory", __VA_ARGS__)\
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ATOMIC_OP_RETURN(_release, , , l, "memory", __VA_ARGS__)\
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ATOMIC_FETCH_OP ( , dmb ish, , l, "memory", __VA_ARGS__)\
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ATOMIC_FETCH_OP (_relaxed, , , , , __VA_ARGS__)\
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ATOMIC_FETCH_OP (_acquire, , a, , "memory", __VA_ARGS__)\
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ATOMIC_FETCH_OP (_release, , , l, "memory", __VA_ARGS__)
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ATOMIC_OPS(add, add)
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ATOMIC_OPS(sub, sub)
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(...) \
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ATOMIC_OP(__VA_ARGS__) \
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ATOMIC_FETCH_OP ( , dmb ish, , l, "memory", __VA_ARGS__)\
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ATOMIC_FETCH_OP (_relaxed, , , , , __VA_ARGS__)\
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ATOMIC_FETCH_OP (_acquire, , a, , "memory", __VA_ARGS__)\
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ATOMIC_FETCH_OP (_release, , , l, "memory", __VA_ARGS__)
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ATOMIC_OPS(and, and)
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ATOMIC_OPS(andnot, bic)
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ATOMIC_OPS(or, orr)
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ATOMIC_OPS(xor, eor)
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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#define ATOMIC64_OP(op, asm_op) \
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__LL_SC_INLINE void \
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__LL_SC_PREFIX(atomic64_##op(long i, atomic64_t *v)) \
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{ \
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long result; \
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unsigned long tmp; \
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\
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asm volatile("// atomic64_" #op "\n" \
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" prfm pstl1strm, %2\n" \
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"1: ldxr %0, %2\n" \
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" " #asm_op " %0, %0, %3\n" \
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" stxr %w1, %0, %2\n" \
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" cbnz %w1, 1b" \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i)); \
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} \
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__LL_SC_EXPORT(atomic64_##op);
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#define ATOMIC64_OP_RETURN(name, mb, acq, rel, cl, op, asm_op) \
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__LL_SC_INLINE long \
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__LL_SC_PREFIX(atomic64_##op##_return##name(long i, atomic64_t *v)) \
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{ \
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long result; \
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unsigned long tmp; \
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\
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asm volatile("// atomic64_" #op "_return" #name "\n" \
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" prfm pstl1strm, %2\n" \
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"1: ld" #acq "xr %0, %2\n" \
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" " #asm_op " %0, %0, %3\n" \
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" st" #rel "xr %w1, %0, %2\n" \
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" cbnz %w1, 1b\n" \
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" " #mb \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i) \
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: cl); \
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\
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return result; \
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} \
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__LL_SC_EXPORT(atomic64_##op##_return##name);
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#define ATOMIC64_FETCH_OP(name, mb, acq, rel, cl, op, asm_op) \
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__LL_SC_INLINE long \
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__LL_SC_PREFIX(atomic64_fetch_##op##name(long i, atomic64_t *v)) \
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{ \
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long result, val; \
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unsigned long tmp; \
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\
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asm volatile("// atomic64_fetch_" #op #name "\n" \
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" prfm pstl1strm, %3\n" \
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"1: ld" #acq "xr %0, %3\n" \
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" " #asm_op " %1, %0, %4\n" \
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" st" #rel "xr %w2, %1, %3\n" \
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" cbnz %w2, 1b\n" \
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" " #mb \
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: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i) \
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: cl); \
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\
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return result; \
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} \
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__LL_SC_EXPORT(atomic64_fetch_##op##name);
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#define ATOMIC64_OPS(...) \
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ATOMIC64_OP(__VA_ARGS__) \
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ATOMIC64_OP_RETURN(, dmb ish, , l, "memory", __VA_ARGS__) \
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ATOMIC64_OP_RETURN(_relaxed,, , , , __VA_ARGS__) \
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ATOMIC64_OP_RETURN(_acquire,, a, , "memory", __VA_ARGS__) \
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ATOMIC64_OP_RETURN(_release,, , l, "memory", __VA_ARGS__) \
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ATOMIC64_FETCH_OP (, dmb ish, , l, "memory", __VA_ARGS__) \
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ATOMIC64_FETCH_OP (_relaxed,, , , , __VA_ARGS__) \
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ATOMIC64_FETCH_OP (_acquire,, a, , "memory", __VA_ARGS__) \
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ATOMIC64_FETCH_OP (_release,, , l, "memory", __VA_ARGS__)
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ATOMIC64_OPS(add, add)
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ATOMIC64_OPS(sub, sub)
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#undef ATOMIC64_OPS
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#define ATOMIC64_OPS(...) \
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ATOMIC64_OP(__VA_ARGS__) \
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ATOMIC64_FETCH_OP (, dmb ish, , l, "memory", __VA_ARGS__) \
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ATOMIC64_FETCH_OP (_relaxed,, , , , __VA_ARGS__) \
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ATOMIC64_FETCH_OP (_acquire,, a, , "memory", __VA_ARGS__) \
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ATOMIC64_FETCH_OP (_release,, , l, "memory", __VA_ARGS__)
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ATOMIC64_OPS(and, and)
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ATOMIC64_OPS(andnot, bic)
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ATOMIC64_OPS(or, orr)
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ATOMIC64_OPS(xor, eor)
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#undef ATOMIC64_OPS
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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__LL_SC_INLINE long
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__LL_SC_PREFIX(atomic64_dec_if_positive(atomic64_t *v))
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{
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long result;
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unsigned long tmp;
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asm volatile("// atomic64_dec_if_positive\n"
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" prfm pstl1strm, %2\n"
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"1: ldxr %0, %2\n"
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" subs %0, %0, #1\n"
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" b.lt 2f\n"
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" stlxr %w1, %0, %2\n"
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" cbnz %w1, 1b\n"
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" dmb ish\n"
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"2:"
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
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:
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: "cc", "memory");
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return result;
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}
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__LL_SC_EXPORT(atomic64_dec_if_positive);
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#define __CMPXCHG_CASE(w, sz, name, mb, acq, rel, cl) \
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__LL_SC_INLINE unsigned long \
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__LL_SC_PREFIX(__cmpxchg_case_##name(volatile void *ptr, \
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unsigned long old, \
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unsigned long new)) \
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{ \
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unsigned long tmp, oldval; \
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\
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asm volatile( \
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" prfm pstl1strm, %[v]\n" \
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"1: ld" #acq "xr" #sz "\t%" #w "[oldval], %[v]\n" \
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" eor %" #w "[tmp], %" #w "[oldval], %" #w "[old]\n" \
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" cbnz %" #w "[tmp], 2f\n" \
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" st" #rel "xr" #sz "\t%w[tmp], %" #w "[new], %[v]\n" \
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" cbnz %w[tmp], 1b\n" \
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" " #mb "\n" \
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"2:" \
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: [tmp] "=&r" (tmp), [oldval] "=&r" (oldval), \
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[v] "+Q" (*(unsigned long *)ptr) \
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: [old] "Lr" (old), [new] "r" (new) \
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: cl); \
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\
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return oldval; \
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} \
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__LL_SC_EXPORT(__cmpxchg_case_##name);
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__CMPXCHG_CASE(w, b, 1, , , , )
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__CMPXCHG_CASE(w, h, 2, , , , )
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__CMPXCHG_CASE(w, , 4, , , , )
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__CMPXCHG_CASE( , , 8, , , , )
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__CMPXCHG_CASE(w, b, acq_1, , a, , "memory")
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__CMPXCHG_CASE(w, h, acq_2, , a, , "memory")
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__CMPXCHG_CASE(w, , acq_4, , a, , "memory")
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__CMPXCHG_CASE( , , acq_8, , a, , "memory")
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__CMPXCHG_CASE(w, b, rel_1, , , l, "memory")
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__CMPXCHG_CASE(w, h, rel_2, , , l, "memory")
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__CMPXCHG_CASE(w, , rel_4, , , l, "memory")
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__CMPXCHG_CASE( , , rel_8, , , l, "memory")
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__CMPXCHG_CASE(w, b, mb_1, dmb ish, , l, "memory")
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__CMPXCHG_CASE(w, h, mb_2, dmb ish, , l, "memory")
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__CMPXCHG_CASE(w, , mb_4, dmb ish, , l, "memory")
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__CMPXCHG_CASE( , , mb_8, dmb ish, , l, "memory")
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#undef __CMPXCHG_CASE
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#define __CMPXCHG_DBL(name, mb, rel, cl) \
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__LL_SC_INLINE long \
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__LL_SC_PREFIX(__cmpxchg_double##name(unsigned long old1, \
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unsigned long old2, \
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unsigned long new1, \
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unsigned long new2, \
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volatile void *ptr)) \
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{ \
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unsigned long tmp, ret; \
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\
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asm volatile("// __cmpxchg_double" #name "\n" \
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" prfm pstl1strm, %2\n" \
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"1: ldxp %0, %1, %2\n" \
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" eor %0, %0, %3\n" \
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" eor %1, %1, %4\n" \
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" orr %1, %0, %1\n" \
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" cbnz %1, 2f\n" \
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" st" #rel "xp %w0, %5, %6, %2\n" \
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" cbnz %w0, 1b\n" \
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" " #mb "\n" \
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"2:" \
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: "=&r" (tmp), "=&r" (ret), "+Q" (*(unsigned long *)ptr) \
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: "r" (old1), "r" (old2), "r" (new1), "r" (new2) \
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: cl); \
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\
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return ret; \
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} \
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__LL_SC_EXPORT(__cmpxchg_double##name);
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__CMPXCHG_DBL( , , , )
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__CMPXCHG_DBL(_mb, dmb ish, l, "memory")
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#undef __CMPXCHG_DBL
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#endif /* __ASM_ATOMIC_LL_SC_H */
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