Thierry Reding 11cec15bf3 iommu/tegra-smmu: Parameterize number of TLB lines ... The number of TLB lines was increased from 16 on Tegra30 to 32 on Tegra114 and later. Parameterize the value so that the initial default can be set accordingly. On Tegra30, initializing the value to 32 would effectively disable the TLB and hence cause massive latencies for memory accesses translated through the SMMU. This is especially noticeable for isochronuous clients such as display, whose FIFOs would continuously underrun. Fixes: 8918465163 ("memory: Add NVIDIA Tegra memory controller support") Signed-off-by: Thierry Reding <treding@nvidia.com>		2015-08-13 17:05:28 +02:00
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ahb.h	ARM: tegra: Move includes to include/soc/tegra	2014-07-17 13:26:47 +02:00
common.h	soc/tegra: Implement runtime check for Tegra SoCs	2014-07-17 14:58:41 +02:00
cpuidle.h	ARM: tegra: Move includes to include/soc/tegra	2014-07-17 13:26:47 +02:00
emc.h	memory: tegra: Add EMC (external memory controller) driver	2015-05-05 11:12:17 +02:00
fuse.h	soc/tegra: fuse: Add RAM code reader helper	2015-05-04 14:21:21 +02:00
mc.h	iommu/tegra-smmu: Parameterize number of TLB lines	2015-08-13 17:05:28 +02:00
pm.h	soc/tegra: pmc: restrict compilation of suspend-related support to ARM	2015-01-09 13:41:19 +01:00
pmc.h	soc/tegra: pmc: move to using a restart handler	2015-05-04 14:21:45 +02:00