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6d6770755f
Most infrastructure can be reused, provide separate handling of context offsets and exit codes. Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
825 lines
26 KiB
C
825 lines
26 KiB
C
/*
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* Copyright (C) 2015 Netronome Systems, Inc.
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*
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* This software is dual licensed under the GNU General License Version 2,
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* June 1991 as shown in the file COPYING in the top-level directory of this
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* source tree or the BSD 2-Clause License provided below. You have the
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* option to license this software under the complete terms of either license.
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*
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* The BSD 2-Clause License:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* 1. Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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/*
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* nfp_net.h
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* Declarations for Netronome network device driver.
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* Authors: Jakub Kicinski <jakub.kicinski@netronome.com>
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* Jason McMullan <jason.mcmullan@netronome.com>
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* Rolf Neugebauer <rolf.neugebauer@netronome.com>
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*/
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#ifndef _NFP_NET_H_
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#define _NFP_NET_H_
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#include <linux/interrupt.h>
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#include <linux/netdevice.h>
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#include <linux/pci.h>
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#include <linux/io-64-nonatomic-hi-lo.h>
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#include "nfp_net_ctrl.h"
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#define nn_err(nn, fmt, args...) netdev_err((nn)->netdev, fmt, ## args)
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#define nn_warn(nn, fmt, args...) netdev_warn((nn)->netdev, fmt, ## args)
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#define nn_info(nn, fmt, args...) netdev_info((nn)->netdev, fmt, ## args)
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#define nn_dbg(nn, fmt, args...) netdev_dbg((nn)->netdev, fmt, ## args)
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#define nn_warn_ratelimit(nn, fmt, args...) \
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do { \
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if (unlikely(net_ratelimit())) \
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netdev_warn((nn)->netdev, fmt, ## args); \
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} while (0)
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/* Max time to wait for NFP to respond on updates (in seconds) */
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#define NFP_NET_POLL_TIMEOUT 5
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/* Interval for reading offloaded filter stats */
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#define NFP_NET_STAT_POLL_IVL msecs_to_jiffies(100)
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/* Bar allocation */
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#define NFP_NET_CTRL_BAR 0
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#define NFP_NET_Q0_BAR 2
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#define NFP_NET_Q1_BAR 4 /* OBSOLETE */
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/* Max bits in DMA address */
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#define NFP_NET_MAX_DMA_BITS 40
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/* Default size for MTU and freelist buffer sizes */
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#define NFP_NET_DEFAULT_MTU 1500
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/* Maximum number of bytes prepended to a packet */
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#define NFP_NET_MAX_PREPEND 64
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/* Interrupt definitions */
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#define NFP_NET_NON_Q_VECTORS 2
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#define NFP_NET_IRQ_LSC_IDX 0
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#define NFP_NET_IRQ_EXN_IDX 1
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/* Queue/Ring definitions */
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#define NFP_NET_MAX_TX_RINGS 64 /* Max. # of Tx rings per device */
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#define NFP_NET_MAX_RX_RINGS 64 /* Max. # of Rx rings per device */
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#define NFP_NET_MAX_R_VECS (NFP_NET_MAX_TX_RINGS > NFP_NET_MAX_RX_RINGS ? \
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NFP_NET_MAX_TX_RINGS : NFP_NET_MAX_RX_RINGS)
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#define NFP_NET_MAX_IRQS (NFP_NET_NON_Q_VECTORS + NFP_NET_MAX_R_VECS)
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#define NFP_NET_MIN_TX_DESCS 256 /* Min. # of Tx descs per ring */
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#define NFP_NET_MIN_RX_DESCS 256 /* Min. # of Rx descs per ring */
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#define NFP_NET_MAX_TX_DESCS (256 * 1024) /* Max. # of Tx descs per ring */
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#define NFP_NET_MAX_RX_DESCS (256 * 1024) /* Max. # of Rx descs per ring */
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#define NFP_NET_TX_DESCS_DEFAULT 4096 /* Default # of Tx descs per ring */
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#define NFP_NET_RX_DESCS_DEFAULT 4096 /* Default # of Rx descs per ring */
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#define NFP_NET_FL_BATCH 16 /* Add freelist in this Batch size */
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/* Offload definitions */
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#define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(__be16))
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#define NFP_NET_RX_BUF_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN)
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#define NFP_NET_RX_BUF_NON_DATA (NFP_NET_RX_BUF_HEADROOM + \
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SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
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/* Forward declarations */
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struct nfp_net;
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struct nfp_net_r_vector;
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/* Convenience macro for writing dma address into RX/TX descriptors */
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#define nfp_desc_set_dma_addr(desc, dma_addr) \
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do { \
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__typeof(desc) __d = (desc); \
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dma_addr_t __addr = (dma_addr); \
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\
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__d->dma_addr_lo = cpu_to_le32(lower_32_bits(__addr)); \
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__d->dma_addr_hi = upper_32_bits(__addr) & 0xff; \
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} while (0)
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/* TX descriptor format */
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#define PCIE_DESC_TX_EOP BIT(7)
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#define PCIE_DESC_TX_OFFSET_MASK GENMASK(6, 0)
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#define PCIE_DESC_TX_MSS_MASK GENMASK(13, 0)
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/* Flags in the host TX descriptor */
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#define PCIE_DESC_TX_CSUM BIT(7)
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#define PCIE_DESC_TX_IP4_CSUM BIT(6)
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#define PCIE_DESC_TX_TCP_CSUM BIT(5)
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#define PCIE_DESC_TX_UDP_CSUM BIT(4)
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#define PCIE_DESC_TX_VLAN BIT(3)
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#define PCIE_DESC_TX_LSO BIT(2)
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#define PCIE_DESC_TX_ENCAP BIT(1)
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#define PCIE_DESC_TX_O_IP4_CSUM BIT(0)
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struct nfp_net_tx_desc {
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union {
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struct {
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u8 dma_addr_hi; /* High bits of host buf address */
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__le16 dma_len; /* Length to DMA for this desc */
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u8 offset_eop; /* Offset in buf where pkt starts +
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* highest bit is eop flag.
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*/
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__le32 dma_addr_lo; /* Low 32bit of host buf addr */
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__le16 mss; /* MSS to be used for LSO */
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u8 l4_offset; /* LSO, where the L4 data starts */
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u8 flags; /* TX Flags, see @PCIE_DESC_TX_* */
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__le16 vlan; /* VLAN tag to add if indicated */
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__le16 data_len; /* Length of frame + meta data */
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} __packed;
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__le32 vals[4];
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};
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};
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/**
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* struct nfp_net_tx_buf - software TX buffer descriptor
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* @skb: sk_buff associated with this buffer
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* @dma_addr: DMA mapping address of the buffer
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* @fidx: Fragment index (-1 for the head and [0..nr_frags-1] for frags)
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* @pkt_cnt: Number of packets to be produced out of the skb associated
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* with this buffer (valid only on the head's buffer).
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* Will be 1 for all non-TSO packets.
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* @real_len: Number of bytes which to be produced out of the skb (valid only
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* on the head's buffer). Equal to skb->len for non-TSO packets.
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*/
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struct nfp_net_tx_buf {
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union {
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struct sk_buff *skb;
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void *frag;
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};
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dma_addr_t dma_addr;
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short int fidx;
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u16 pkt_cnt;
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u32 real_len;
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};
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/**
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* struct nfp_net_tx_ring - TX ring structure
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* @r_vec: Back pointer to ring vector structure
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* @idx: Ring index from Linux's perspective
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* @qcidx: Queue Controller Peripheral (QCP) queue index for the TX queue
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* @qcp_q: Pointer to base of the QCP TX queue
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* @cnt: Size of the queue in number of descriptors
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* @wr_p: TX ring write pointer (free running)
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* @rd_p: TX ring read pointer (free running)
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* @qcp_rd_p: Local copy of QCP TX queue read pointer
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* @wr_ptr_add: Accumulated number of buffers to add to QCP write pointer
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* (used for .xmit_more delayed kick)
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* @txbufs: Array of transmitted TX buffers, to free on transmit
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* @txds: Virtual address of TX ring in host memory
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* @dma: DMA address of the TX ring
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* @size: Size, in bytes, of the TX ring (needed to free)
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*/
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struct nfp_net_tx_ring {
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struct nfp_net_r_vector *r_vec;
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u32 idx;
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int qcidx;
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u8 __iomem *qcp_q;
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u32 cnt;
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u32 wr_p;
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u32 rd_p;
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u32 qcp_rd_p;
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u32 wr_ptr_add;
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struct nfp_net_tx_buf *txbufs;
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struct nfp_net_tx_desc *txds;
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dma_addr_t dma;
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unsigned int size;
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} ____cacheline_aligned;
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/* RX and freelist descriptor format */
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#define PCIE_DESC_RX_DD BIT(7)
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#define PCIE_DESC_RX_META_LEN_MASK GENMASK(6, 0)
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/* Flags in the RX descriptor */
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#define PCIE_DESC_RX_RSS cpu_to_le16(BIT(15))
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#define PCIE_DESC_RX_I_IP4_CSUM cpu_to_le16(BIT(14))
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#define PCIE_DESC_RX_I_IP4_CSUM_OK cpu_to_le16(BIT(13))
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#define PCIE_DESC_RX_I_TCP_CSUM cpu_to_le16(BIT(12))
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#define PCIE_DESC_RX_I_TCP_CSUM_OK cpu_to_le16(BIT(11))
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#define PCIE_DESC_RX_I_UDP_CSUM cpu_to_le16(BIT(10))
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#define PCIE_DESC_RX_I_UDP_CSUM_OK cpu_to_le16(BIT(9))
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#define PCIE_DESC_RX_BPF cpu_to_le16(BIT(8))
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#define PCIE_DESC_RX_EOP cpu_to_le16(BIT(7))
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#define PCIE_DESC_RX_IP4_CSUM cpu_to_le16(BIT(6))
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#define PCIE_DESC_RX_IP4_CSUM_OK cpu_to_le16(BIT(5))
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#define PCIE_DESC_RX_TCP_CSUM cpu_to_le16(BIT(4))
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#define PCIE_DESC_RX_TCP_CSUM_OK cpu_to_le16(BIT(3))
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#define PCIE_DESC_RX_UDP_CSUM cpu_to_le16(BIT(2))
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#define PCIE_DESC_RX_UDP_CSUM_OK cpu_to_le16(BIT(1))
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#define PCIE_DESC_RX_VLAN cpu_to_le16(BIT(0))
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#define PCIE_DESC_RX_CSUM_ALL (PCIE_DESC_RX_IP4_CSUM | \
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PCIE_DESC_RX_TCP_CSUM | \
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PCIE_DESC_RX_UDP_CSUM | \
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PCIE_DESC_RX_I_IP4_CSUM | \
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PCIE_DESC_RX_I_TCP_CSUM | \
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PCIE_DESC_RX_I_UDP_CSUM)
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#define PCIE_DESC_RX_CSUM_OK_SHIFT 1
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#define __PCIE_DESC_RX_CSUM_ALL le16_to_cpu(PCIE_DESC_RX_CSUM_ALL)
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#define __PCIE_DESC_RX_CSUM_ALL_OK (__PCIE_DESC_RX_CSUM_ALL >> \
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PCIE_DESC_RX_CSUM_OK_SHIFT)
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struct nfp_net_rx_desc {
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union {
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struct {
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u8 dma_addr_hi; /* High bits of the buf address */
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__le16 reserved; /* Must be zero */
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u8 meta_len_dd; /* Must be zero */
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__le32 dma_addr_lo; /* Low bits of the buffer address */
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} __packed fld;
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struct {
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__le16 data_len; /* Length of the frame + meta data */
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u8 reserved;
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u8 meta_len_dd; /* Length of meta data prepended +
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* descriptor done flag.
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*/
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__le16 flags; /* RX flags. See @PCIE_DESC_RX_* */
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__le16 vlan; /* VLAN if stripped */
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} __packed rxd;
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__le32 vals[2];
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};
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};
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#define NFP_NET_META_FIELD_MASK GENMASK(NFP_NET_META_FIELD_SIZE - 1, 0)
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struct nfp_net_rx_hash {
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__be32 hash_type;
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__be32 hash;
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};
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/**
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* struct nfp_net_rx_buf - software RX buffer descriptor
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* @frag: page fragment buffer
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* @dma_addr: DMA mapping address of the buffer
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*/
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struct nfp_net_rx_buf {
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void *frag;
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dma_addr_t dma_addr;
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};
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/**
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* struct nfp_net_rx_ring - RX ring structure
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* @r_vec: Back pointer to ring vector structure
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* @cnt: Size of the queue in number of descriptors
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* @wr_p: FL/RX ring write pointer (free running)
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* @rd_p: FL/RX ring read pointer (free running)
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* @idx: Ring index from Linux's perspective
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* @fl_qcidx: Queue Controller Peripheral (QCP) queue index for the freelist
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* @rx_qcidx: Queue Controller Peripheral (QCP) queue index for the RX queue
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* @qcp_fl: Pointer to base of the QCP freelist queue
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* @qcp_rx: Pointer to base of the QCP RX queue
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* @wr_ptr_add: Accumulated number of buffers to add to QCP write pointer
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* (used for free list batching)
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* @rxbufs: Array of transmitted FL/RX buffers
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* @rxds: Virtual address of FL/RX ring in host memory
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* @dma: DMA address of the FL/RX ring
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* @size: Size, in bytes, of the FL/RX ring (needed to free)
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* @bufsz: Buffer allocation size for convenience of management routines
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* (NOTE: this is in second cache line, do not use on fast path!)
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*/
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struct nfp_net_rx_ring {
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struct nfp_net_r_vector *r_vec;
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u32 cnt;
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u32 wr_p;
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u32 rd_p;
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u16 idx;
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u16 wr_ptr_add;
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int fl_qcidx;
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int rx_qcidx;
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u8 __iomem *qcp_fl;
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u8 __iomem *qcp_rx;
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struct nfp_net_rx_buf *rxbufs;
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struct nfp_net_rx_desc *rxds;
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dma_addr_t dma;
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unsigned int size;
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unsigned int bufsz;
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} ____cacheline_aligned;
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/**
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* struct nfp_net_r_vector - Per ring interrupt vector configuration
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* @nfp_net: Backpointer to nfp_net structure
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* @napi: NAPI structure for this ring vec
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* @tx_ring: Pointer to TX ring
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* @rx_ring: Pointer to RX ring
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* @xdp_ring: Pointer to an extra TX ring for XDP
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* @irq_idx: Index into MSI-X table
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* @rx_sync: Seqlock for atomic updates of RX stats
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* @rx_pkts: Number of received packets
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* @rx_bytes: Number of received bytes
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* @rx_drops: Number of packets dropped on RX due to lack of resources
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* @hw_csum_rx_ok: Counter of packets where the HW checksum was OK
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* @hw_csum_rx_inner_ok: Counter of packets where the inner HW checksum was OK
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* @hw_csum_rx_error: Counter of packets with bad checksums
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* @tx_sync: Seqlock for atomic updates of TX stats
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* @tx_pkts: Number of Transmitted packets
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* @tx_bytes: Number of Transmitted bytes
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* @hw_csum_tx: Counter of packets with TX checksum offload requested
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* @hw_csum_tx_inner: Counter of inner TX checksum offload requests
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* @tx_gather: Counter of packets with Gather DMA
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* @tx_lso: Counter of LSO packets sent
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* @tx_errors: How many TX errors were encountered
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* @tx_busy: How often was TX busy (no space)?
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* @handler: Interrupt handler for this ring vector
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* @name: Name of the interrupt vector
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* @affinity_mask: SMP affinity mask for this vector
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*
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* This structure ties RX and TX rings to interrupt vectors and a NAPI
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* context. This currently only supports one RX and TX ring per
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* interrupt vector but might be extended in the future to allow
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* association of multiple rings per vector.
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*/
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struct nfp_net_r_vector {
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struct nfp_net *nfp_net;
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struct napi_struct napi;
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struct nfp_net_tx_ring *tx_ring;
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struct nfp_net_rx_ring *rx_ring;
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int irq_idx;
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struct u64_stats_sync rx_sync;
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u64 rx_pkts;
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u64 rx_bytes;
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u64 rx_drops;
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u64 hw_csum_rx_ok;
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u64 hw_csum_rx_inner_ok;
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u64 hw_csum_rx_error;
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struct nfp_net_tx_ring *xdp_ring;
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struct u64_stats_sync tx_sync;
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u64 tx_pkts;
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u64 tx_bytes;
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u64 hw_csum_tx;
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u64 hw_csum_tx_inner;
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u64 tx_gather;
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u64 tx_lso;
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u64 tx_errors;
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u64 tx_busy;
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irq_handler_t handler;
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char name[IFNAMSIZ + 8];
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cpumask_t affinity_mask;
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} ____cacheline_aligned;
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/* Firmware version as it is written in the 32bit value in the BAR */
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struct nfp_net_fw_version {
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u8 minor;
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u8 major;
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u8 class;
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u8 resv;
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} __packed;
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static inline bool nfp_net_fw_ver_eq(struct nfp_net_fw_version *fw_ver,
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u8 resv, u8 class, u8 major, u8 minor)
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{
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return fw_ver->resv == resv &&
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fw_ver->class == class &&
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fw_ver->major == major &&
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fw_ver->minor == minor;
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}
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struct nfp_stat_pair {
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u64 pkts;
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u64 bytes;
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};
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/**
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* struct nfp_net - NFP network device structure
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* @pdev: Backpointer to PCI device
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* @netdev: Backpointer to net_device structure
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* @nfp_fallback: Is the driver used in fallback mode?
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* @is_vf: Is the driver attached to a VF?
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* @fw_loaded: Is the firmware loaded?
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* @bpf_offload_skip_sw: Offloaded BPF program will not be rerun by cls_bpf
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* @bpf_offload_xdp: Offloaded BPF program is XDP
|
|
* @ctrl: Local copy of the control register/word.
|
|
* @fl_bufsz: Currently configured size of the freelist buffers
|
|
* @rx_offset: Offset in the RX buffers where packet data starts
|
|
* @xdp_prog: Installed XDP program
|
|
* @cpp: Pointer to the CPP handle
|
|
* @nfp_dev_cpp: Pointer to the NFP Device handle
|
|
* @ctrl_area: Pointer to the CPP area for the control BAR
|
|
* @tx_area: Pointer to the CPP area for the TX queues
|
|
* @rx_area: Pointer to the CPP area for the FL/RX queues
|
|
* @fw_ver: Firmware version
|
|
* @cap: Capabilities advertised by the Firmware
|
|
* @max_mtu: Maximum support MTU advertised by the Firmware
|
|
* @rss_cfg: RSS configuration
|
|
* @rss_key: RSS secret key
|
|
* @rss_itbl: RSS indirection table
|
|
* @rx_filter: Filter offload statistics - dropped packets/bytes
|
|
* @rx_filter_prev: Filter offload statistics - values from previous update
|
|
* @rx_filter_change: Jiffies when statistics last changed
|
|
* @rx_filter_stats_timer: Timer for polling filter offload statistics
|
|
* @rx_filter_lock: Lock protecting timer state changes (teardown)
|
|
* @max_tx_rings: Maximum number of TX rings supported by the Firmware
|
|
* @max_rx_rings: Maximum number of RX rings supported by the Firmware
|
|
* @num_tx_rings: Currently configured number of TX rings
|
|
* @num_stack_tx_rings: Number of TX rings used by the stack (not XDP)
|
|
* @num_rx_rings: Currently configured number of RX rings
|
|
* @txd_cnt: Size of the TX ring in number of descriptors
|
|
* @rxd_cnt: Size of the RX ring in number of descriptors
|
|
* @tx_rings: Array of pre-allocated TX ring structures
|
|
* @rx_rings: Array of pre-allocated RX ring structures
|
|
* @max_r_vecs: Number of allocated interrupt vectors for RX/TX
|
|
* @num_r_vecs: Number of used ring vectors
|
|
* @r_vecs: Pre-allocated array of ring vectors
|
|
* @irq_entries: Pre-allocated array of MSI-X entries
|
|
* @lsc_handler: Handler for Link State Change interrupt
|
|
* @lsc_name: Name for Link State Change interrupt
|
|
* @exn_handler: Handler for Exception interrupt
|
|
* @exn_name: Name for Exception interrupt
|
|
* @shared_handler: Handler for shared interrupts
|
|
* @shared_name: Name for shared interrupt
|
|
* @me_freq_mhz: ME clock_freq (MHz)
|
|
* @reconfig_lock: Protects HW reconfiguration request regs/machinery
|
|
* @reconfig_posted: Pending reconfig bits coming from async sources
|
|
* @reconfig_timer_active: Timer for reading reconfiguration results is pending
|
|
* @reconfig_sync_present: Some thread is performing synchronous reconfig
|
|
* @reconfig_timer: Timer for async reading of reconfig results
|
|
* @link_up: Is the link up?
|
|
* @link_status_lock: Protects @link_up and ensures atomicity with BAR reading
|
|
* @rx_coalesce_usecs: RX interrupt moderation usecs delay parameter
|
|
* @rx_coalesce_max_frames: RX interrupt moderation frame count parameter
|
|
* @tx_coalesce_usecs: TX interrupt moderation usecs delay parameter
|
|
* @tx_coalesce_max_frames: TX interrupt moderation frame count parameter
|
|
* @vxlan_ports: VXLAN ports for RX inner csum offload communicated to HW
|
|
* @vxlan_usecnt: IPv4/IPv6 VXLAN port use counts
|
|
* @qcp_cfg: Pointer to QCP queue used for configuration notification
|
|
* @ctrl_bar: Pointer to mapped control BAR
|
|
* @tx_bar: Pointer to mapped TX queues
|
|
* @rx_bar: Pointer to mapped FL/RX queues
|
|
* @debugfs_dir: Device directory in debugfs
|
|
*/
|
|
struct nfp_net {
|
|
struct pci_dev *pdev;
|
|
struct net_device *netdev;
|
|
|
|
unsigned nfp_fallback:1;
|
|
unsigned is_vf:1;
|
|
unsigned fw_loaded:1;
|
|
unsigned bpf_offload_skip_sw:1;
|
|
unsigned bpf_offload_xdp:1;
|
|
|
|
u32 ctrl;
|
|
u32 fl_bufsz;
|
|
|
|
u32 rx_offset;
|
|
|
|
struct bpf_prog *xdp_prog;
|
|
|
|
struct nfp_net_tx_ring *tx_rings;
|
|
struct nfp_net_rx_ring *rx_rings;
|
|
|
|
#ifdef CONFIG_PCI_IOV
|
|
unsigned int num_vfs;
|
|
struct vf_data_storage *vfinfo;
|
|
int vf_rate_link_speed;
|
|
#endif
|
|
|
|
struct nfp_cpp *cpp;
|
|
struct platform_device *nfp_dev_cpp;
|
|
struct nfp_cpp_area *ctrl_area;
|
|
struct nfp_cpp_area *tx_area;
|
|
struct nfp_cpp_area *rx_area;
|
|
|
|
struct nfp_net_fw_version fw_ver;
|
|
u32 cap;
|
|
u32 max_mtu;
|
|
|
|
u32 rss_cfg;
|
|
u8 rss_key[NFP_NET_CFG_RSS_KEY_SZ];
|
|
u8 rss_itbl[NFP_NET_CFG_RSS_ITBL_SZ];
|
|
|
|
struct nfp_stat_pair rx_filter, rx_filter_prev;
|
|
unsigned long rx_filter_change;
|
|
struct timer_list rx_filter_stats_timer;
|
|
spinlock_t rx_filter_lock;
|
|
|
|
unsigned int max_tx_rings;
|
|
unsigned int max_rx_rings;
|
|
|
|
unsigned int num_tx_rings;
|
|
unsigned int num_stack_tx_rings;
|
|
unsigned int num_rx_rings;
|
|
|
|
int stride_tx;
|
|
int stride_rx;
|
|
|
|
int txd_cnt;
|
|
int rxd_cnt;
|
|
|
|
unsigned int max_r_vecs;
|
|
unsigned int num_r_vecs;
|
|
struct nfp_net_r_vector r_vecs[NFP_NET_MAX_R_VECS];
|
|
struct msix_entry irq_entries[NFP_NET_MAX_IRQS];
|
|
|
|
irq_handler_t lsc_handler;
|
|
char lsc_name[IFNAMSIZ + 8];
|
|
|
|
irq_handler_t exn_handler;
|
|
char exn_name[IFNAMSIZ + 8];
|
|
|
|
irq_handler_t shared_handler;
|
|
char shared_name[IFNAMSIZ + 8];
|
|
|
|
u32 me_freq_mhz;
|
|
|
|
bool link_up;
|
|
spinlock_t link_status_lock;
|
|
|
|
spinlock_t reconfig_lock;
|
|
u32 reconfig_posted;
|
|
bool reconfig_timer_active;
|
|
bool reconfig_sync_present;
|
|
struct timer_list reconfig_timer;
|
|
|
|
u32 rx_coalesce_usecs;
|
|
u32 rx_coalesce_max_frames;
|
|
u32 tx_coalesce_usecs;
|
|
u32 tx_coalesce_max_frames;
|
|
|
|
__be16 vxlan_ports[NFP_NET_N_VXLAN_PORTS];
|
|
u8 vxlan_usecnt[NFP_NET_N_VXLAN_PORTS];
|
|
|
|
u8 __iomem *qcp_cfg;
|
|
|
|
u8 __iomem *ctrl_bar;
|
|
u8 __iomem *q_bar;
|
|
u8 __iomem *tx_bar;
|
|
u8 __iomem *rx_bar;
|
|
|
|
struct dentry *debugfs_dir;
|
|
};
|
|
|
|
struct nfp_net_ring_set {
|
|
unsigned int n_rings;
|
|
unsigned int mtu;
|
|
unsigned int dcnt;
|
|
void *rings;
|
|
};
|
|
|
|
/* Functions to read/write from/to a BAR
|
|
* Performs any endian conversion necessary.
|
|
*/
|
|
static inline u16 nn_readb(struct nfp_net *nn, int off)
|
|
{
|
|
return readb(nn->ctrl_bar + off);
|
|
}
|
|
|
|
static inline void nn_writeb(struct nfp_net *nn, int off, u8 val)
|
|
{
|
|
writeb(val, nn->ctrl_bar + off);
|
|
}
|
|
|
|
static inline u16 nn_readw(struct nfp_net *nn, int off)
|
|
{
|
|
return readw(nn->ctrl_bar + off);
|
|
}
|
|
|
|
static inline void nn_writew(struct nfp_net *nn, int off, u16 val)
|
|
{
|
|
writew(val, nn->ctrl_bar + off);
|
|
}
|
|
|
|
static inline u32 nn_readl(struct nfp_net *nn, int off)
|
|
{
|
|
return readl(nn->ctrl_bar + off);
|
|
}
|
|
|
|
static inline void nn_writel(struct nfp_net *nn, int off, u32 val)
|
|
{
|
|
writel(val, nn->ctrl_bar + off);
|
|
}
|
|
|
|
static inline u64 nn_readq(struct nfp_net *nn, int off)
|
|
{
|
|
return readq(nn->ctrl_bar + off);
|
|
}
|
|
|
|
static inline void nn_writeq(struct nfp_net *nn, int off, u64 val)
|
|
{
|
|
writeq(val, nn->ctrl_bar + off);
|
|
}
|
|
|
|
/* Flush posted PCI writes by reading something without side effects */
|
|
static inline void nn_pci_flush(struct nfp_net *nn)
|
|
{
|
|
nn_readl(nn, NFP_NET_CFG_VERSION);
|
|
}
|
|
|
|
/* Queue Controller Peripheral access functions and definitions.
|
|
*
|
|
* Some of the BARs of the NFP are mapped to portions of the Queue
|
|
* Controller Peripheral (QCP) address space on the NFP. A QCP queue
|
|
* has a read and a write pointer (as well as a size and flags,
|
|
* indicating overflow etc). The QCP offers a number of different
|
|
* operation on queue pointers, but here we only offer function to
|
|
* either add to a pointer or to read the pointer value.
|
|
*/
|
|
#define NFP_QCP_QUEUE_ADDR_SZ 0x800
|
|
#define NFP_QCP_QUEUE_OFF(_x) ((_x) * NFP_QCP_QUEUE_ADDR_SZ)
|
|
#define NFP_QCP_QUEUE_ADD_RPTR 0x0000
|
|
#define NFP_QCP_QUEUE_ADD_WPTR 0x0004
|
|
#define NFP_QCP_QUEUE_STS_LO 0x0008
|
|
#define NFP_QCP_QUEUE_STS_LO_READPTR_mask 0x3ffff
|
|
#define NFP_QCP_QUEUE_STS_HI 0x000c
|
|
#define NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask 0x3ffff
|
|
|
|
/* The offset of a QCP queues in the PCIe Target */
|
|
#define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
|
|
|
|
/* nfp_qcp_ptr - Read or Write Pointer of a queue */
|
|
enum nfp_qcp_ptr {
|
|
NFP_QCP_READ_PTR = 0,
|
|
NFP_QCP_WRITE_PTR
|
|
};
|
|
|
|
/* There appear to be an *undocumented* upper limit on the value which
|
|
* one can add to a queue and that value is either 0x3f or 0x7f. We
|
|
* go with 0x3f as a conservative measure.
|
|
*/
|
|
#define NFP_QCP_MAX_ADD 0x3f
|
|
|
|
static inline void _nfp_qcp_ptr_add(u8 __iomem *q,
|
|
enum nfp_qcp_ptr ptr, u32 val)
|
|
{
|
|
u32 off;
|
|
|
|
if (ptr == NFP_QCP_READ_PTR)
|
|
off = NFP_QCP_QUEUE_ADD_RPTR;
|
|
else
|
|
off = NFP_QCP_QUEUE_ADD_WPTR;
|
|
|
|
while (val > NFP_QCP_MAX_ADD) {
|
|
writel(NFP_QCP_MAX_ADD, q + off);
|
|
val -= NFP_QCP_MAX_ADD;
|
|
}
|
|
|
|
writel(val, q + off);
|
|
}
|
|
|
|
/**
|
|
* nfp_qcp_rd_ptr_add() - Add the value to the read pointer of a queue
|
|
*
|
|
* @q: Base address for queue structure
|
|
* @val: Value to add to the queue pointer
|
|
*
|
|
* If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
|
|
*/
|
|
static inline void nfp_qcp_rd_ptr_add(u8 __iomem *q, u32 val)
|
|
{
|
|
_nfp_qcp_ptr_add(q, NFP_QCP_READ_PTR, val);
|
|
}
|
|
|
|
/**
|
|
* nfp_qcp_wr_ptr_add() - Add the value to the write pointer of a queue
|
|
*
|
|
* @q: Base address for queue structure
|
|
* @val: Value to add to the queue pointer
|
|
*
|
|
* If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
|
|
*/
|
|
static inline void nfp_qcp_wr_ptr_add(u8 __iomem *q, u32 val)
|
|
{
|
|
_nfp_qcp_ptr_add(q, NFP_QCP_WRITE_PTR, val);
|
|
}
|
|
|
|
static inline u32 _nfp_qcp_read(u8 __iomem *q, enum nfp_qcp_ptr ptr)
|
|
{
|
|
u32 off;
|
|
u32 val;
|
|
|
|
if (ptr == NFP_QCP_READ_PTR)
|
|
off = NFP_QCP_QUEUE_STS_LO;
|
|
else
|
|
off = NFP_QCP_QUEUE_STS_HI;
|
|
|
|
val = readl(q + off);
|
|
|
|
if (ptr == NFP_QCP_READ_PTR)
|
|
return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
|
|
else
|
|
return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
|
|
}
|
|
|
|
/**
|
|
* nfp_qcp_rd_ptr_read() - Read the current read pointer value for a queue
|
|
* @q: Base address for queue structure
|
|
*
|
|
* Return: Value read.
|
|
*/
|
|
static inline u32 nfp_qcp_rd_ptr_read(u8 __iomem *q)
|
|
{
|
|
return _nfp_qcp_read(q, NFP_QCP_READ_PTR);
|
|
}
|
|
|
|
/**
|
|
* nfp_qcp_wr_ptr_read() - Read the current write pointer value for a queue
|
|
* @q: Base address for queue structure
|
|
*
|
|
* Return: Value read.
|
|
*/
|
|
static inline u32 nfp_qcp_wr_ptr_read(u8 __iomem *q)
|
|
{
|
|
return _nfp_qcp_read(q, NFP_QCP_WRITE_PTR);
|
|
}
|
|
|
|
/* Globals */
|
|
extern const char nfp_net_driver_name[];
|
|
extern const char nfp_net_driver_version[];
|
|
|
|
/* Prototypes */
|
|
void nfp_net_get_fw_version(struct nfp_net_fw_version *fw_ver,
|
|
void __iomem *ctrl_bar);
|
|
|
|
struct nfp_net *
|
|
nfp_net_netdev_alloc(struct pci_dev *pdev,
|
|
unsigned int max_tx_rings, unsigned int max_rx_rings);
|
|
void nfp_net_netdev_free(struct nfp_net *nn);
|
|
int nfp_net_netdev_init(struct net_device *netdev);
|
|
void nfp_net_netdev_clean(struct net_device *netdev);
|
|
void nfp_net_set_ethtool_ops(struct net_device *netdev);
|
|
void nfp_net_info(struct nfp_net *nn);
|
|
int nfp_net_reconfig(struct nfp_net *nn, u32 update);
|
|
void nfp_net_rss_write_itbl(struct nfp_net *nn);
|
|
void nfp_net_rss_write_key(struct nfp_net *nn);
|
|
void nfp_net_coalesce_write_cfg(struct nfp_net *nn);
|
|
int nfp_net_irqs_alloc(struct nfp_net *nn);
|
|
void nfp_net_irqs_disable(struct nfp_net *nn);
|
|
int
|
|
nfp_net_ring_reconfig(struct nfp_net *nn, struct bpf_prog **xdp_prog,
|
|
struct nfp_net_ring_set *rx, struct nfp_net_ring_set *tx);
|
|
|
|
#ifdef CONFIG_NFP_NET_DEBUG
|
|
void nfp_net_debugfs_create(void);
|
|
void nfp_net_debugfs_destroy(void);
|
|
void nfp_net_debugfs_adapter_add(struct nfp_net *nn);
|
|
void nfp_net_debugfs_adapter_del(struct nfp_net *nn);
|
|
#else
|
|
static inline void nfp_net_debugfs_create(void)
|
|
{
|
|
}
|
|
|
|
static inline void nfp_net_debugfs_destroy(void)
|
|
{
|
|
}
|
|
|
|
static inline void nfp_net_debugfs_adapter_add(struct nfp_net *nn)
|
|
{
|
|
}
|
|
|
|
static inline void nfp_net_debugfs_adapter_del(struct nfp_net *nn)
|
|
{
|
|
}
|
|
#endif /* CONFIG_NFP_NET_DEBUG */
|
|
|
|
void nfp_net_filter_stats_timer(unsigned long data);
|
|
int nfp_net_bpf_offload(struct nfp_net *nn, struct tc_cls_bpf_offload *cls_bpf);
|
|
|
|
#endif /* _NFP_NET_H_ */
|