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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7725ccfda5
Add new driver for Brocade Hardware Signed-off-by: Jing Huang <huangj@brocade.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
143 lines
3.5 KiB
C
143 lines
3.5 KiB
C
/*
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* Copyright (c) 2005-2009 Brocade Communications Systems, Inc.
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* All rights reserved
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* www.brocade.com
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*
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* Linux driver for Brocade Fibre Channel Host Bus Adapter.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License (GPL) Version 2 as
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* published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <bfa_priv.h>
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#include <bfi/bfi_cbreg.h>
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void
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bfa_hwcb_reginit(struct bfa_s *bfa)
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{
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struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
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bfa_os_addr_t kva = bfa_ioc_bar0(&bfa->ioc);
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int i, q, fn = bfa_ioc_pcifn(&bfa->ioc);
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if (fn == 0) {
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bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
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bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK);
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} else {
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bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
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bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
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}
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for (i = 0; i < BFI_IOC_MAX_CQS; i++) {
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/*
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* CPE registers
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*/
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q = CPE_Q_NUM(fn, i);
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bfa_regs->cpe_q_pi[i] = (kva + CPE_Q_PI(q));
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bfa_regs->cpe_q_ci[i] = (kva + CPE_Q_CI(q));
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bfa_regs->cpe_q_depth[i] = (kva + CPE_Q_DEPTH(q));
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/*
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* RME registers
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*/
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q = CPE_Q_NUM(fn, i);
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bfa_regs->rme_q_pi[i] = (kva + RME_Q_PI(q));
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bfa_regs->rme_q_ci[i] = (kva + RME_Q_CI(q));
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bfa_regs->rme_q_depth[i] = (kva + RME_Q_DEPTH(q));
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}
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}
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void
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bfa_hwcb_rspq_ack(struct bfa_s *bfa, int rspq)
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{
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}
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static void
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bfa_hwcb_rspq_ack_msix(struct bfa_s *bfa, int rspq)
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{
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bfa_reg_write(bfa->iocfc.bfa_regs.intr_status,
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__HFN_INT_RME_Q0 << RME_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), rspq));
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}
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void
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bfa_hwcb_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
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u32 *num_vecs, u32 *max_vec_bit)
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{
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#define __HFN_NUMINTS 13
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if (bfa_ioc_pcifn(&bfa->ioc) == 0) {
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*msix_vecs_bmap = (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 |
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__HFN_INT_CPE_Q2 | __HFN_INT_CPE_Q3 |
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__HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 |
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__HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 |
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__HFN_INT_MBOX_LPU0);
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*max_vec_bit = __HFN_INT_MBOX_LPU0;
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} else {
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*msix_vecs_bmap = (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 |
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__HFN_INT_CPE_Q6 | __HFN_INT_CPE_Q7 |
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__HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 |
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__HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 |
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__HFN_INT_MBOX_LPU1);
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*max_vec_bit = __HFN_INT_MBOX_LPU1;
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}
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*msix_vecs_bmap |= (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 |
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__HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS);
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*num_vecs = __HFN_NUMINTS;
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}
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/**
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* No special setup required for crossbow -- vector assignments are implicit.
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*/
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void
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bfa_hwcb_msix_init(struct bfa_s *bfa, int nvecs)
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{
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int i;
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bfa_assert((nvecs == 1) || (nvecs == __HFN_NUMINTS));
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bfa->msix.nvecs = nvecs;
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if (nvecs == 1) {
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for (i = 0; i < BFA_MSIX_CB_MAX; i++)
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bfa->msix.handler[i] = bfa_msix_all;
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return;
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}
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for (i = BFA_MSIX_CPE_Q0; i <= BFA_MSIX_CPE_Q7; i++)
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bfa->msix.handler[i] = bfa_msix_reqq;
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for (i = BFA_MSIX_RME_Q0; i <= BFA_MSIX_RME_Q7; i++)
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bfa->msix.handler[i] = bfa_msix_rspq;
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for (; i < BFA_MSIX_CB_MAX; i++)
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bfa->msix.handler[i] = bfa_msix_lpu_err;
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}
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/**
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* Crossbow -- dummy, interrupts are masked
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*/
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void
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bfa_hwcb_msix_install(struct bfa_s *bfa)
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{
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}
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void
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bfa_hwcb_msix_uninstall(struct bfa_s *bfa)
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{
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}
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/**
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* No special enable/disable -- vector assignments are implicit.
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*/
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void
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bfa_hwcb_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
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{
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bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack_msix;
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}
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