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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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100f5f7fbc
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
v2: Fix 32-bit build
v3: Use new helper function in SSEU workaround warning message
v4: Use GEM_BUG_ON to force developers to use valid SSEU configurations
per platform (Chris)
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190823160307.180813-12-stuart.summers@intel.com
106 lines
2.6 KiB
C
106 lines
2.6 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_SSEU_H__
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#define __INTEL_SSEU_H__
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include "i915_gem.h"
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struct drm_i915_private;
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#define GEN_MAX_SLICES (6) /* CNL upper bound */
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#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
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#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
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#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
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#define GEN_MAX_EUS (10) /* HSW upper bound */
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#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
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struct sseu_dev_info {
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u8 slice_mask;
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u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
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u16 eu_total;
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u8 eu_per_subslice;
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u8 min_eu_in_pool;
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/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
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u8 subslice_7eu[3];
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u8 has_slice_pg:1;
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u8 has_subslice_pg:1;
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u8 has_eu_pg:1;
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/* Topology fields */
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u8 max_slices;
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u8 max_subslices;
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u8 max_eus_per_subslice;
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u8 ss_stride;
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u8 eu_stride;
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/* We don't have more than 8 eus per subslice at the moment and as we
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* store eus enabled using bits, no need to multiply by eus per
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* subslice.
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*/
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u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
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};
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/*
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* Powergating configuration for a particular (context,engine).
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*/
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struct intel_sseu {
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u8 slice_mask;
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u8 subslice_mask;
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u8 min_eus_per_subslice;
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u8 max_eus_per_subslice;
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};
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static inline struct intel_sseu
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intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
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{
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struct intel_sseu value = {
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.slice_mask = sseu->slice_mask,
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.subslice_mask = sseu->subslice_mask[0],
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.min_eus_per_subslice = sseu->max_eus_per_subslice,
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.max_eus_per_subslice = sseu->max_eus_per_subslice,
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};
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return value;
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}
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static inline bool
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intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
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int subslice)
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{
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u8 mask;
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int ss_idx = subslice / BITS_PER_BYTE;
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GEM_BUG_ON(ss_idx >= sseu->ss_stride);
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mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
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return mask & BIT(subslice % BITS_PER_BYTE);
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}
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void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
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u8 max_subslices, u8 max_eus_per_subslice);
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unsigned int
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intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
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unsigned int
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intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
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u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
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void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
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u32 ss_mask);
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u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
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const struct intel_sseu *req_sseu);
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#endif /* __INTEL_SSEU_H__ */
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