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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1191ccb34c
write{b,w,l,q}_relaxed are implemented by some architectures in order to
permit memory-mapped I/O accesses with weaker barrier semantics than the
non-relaxed variants.
This patch adds dummy macros for the write accessors to sparc, in the
same vein as the dummy definitions for the relaxed read accessors. The
existing relaxed read{b,w,l} accessors are moved into asm/io.h, since
they are identical between 32-bit and 64-bit machines.
Acked-by: "David S. Miller" <davem@davemloft.net>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
448 lines
10 KiB
C
448 lines
10 KiB
C
#ifndef __SPARC64_IO_H
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#define __SPARC64_IO_H
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/page.h> /* IO address mapping routines need this */
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#include <asm/asi.h>
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#include <asm-generic/pci_iomap.h>
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/* BIO layer definitions. */
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extern unsigned long kern_base, kern_size;
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/* __raw_{read,write}{b,w,l,q} uses direct access.
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* Access the memory as big endian bypassing the cache
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* by using ASI_PHYS_BYPASS_EC_E
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*/
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#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 ret;
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__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 ret;
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__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 ret;
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__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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#define __raw_readq __raw_readq
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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u64 ret;
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__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 b, const volatile void __iomem *addr)
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{
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__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
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: /* no outputs */
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: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 w, const volatile void __iomem *addr)
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{
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__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
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: /* no outputs */
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: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 l, const volatile void __iomem *addr)
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{
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__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
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: /* no outputs */
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: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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#define __raw_writeq __raw_writeq
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static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
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{
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__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
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: /* no outputs */
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: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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/* Memory functions, same as I/O accesses on Ultra.
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* Access memory as little endian bypassing
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* the cache by using ASI_PHYS_BYPASS_EC_E_L
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*/
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#define readb readb
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static inline u8 readb(const volatile void __iomem *addr)
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{ u8 ret;
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__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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return ret;
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}
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#define readw readw
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static inline u16 readw(const volatile void __iomem *addr)
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{ u16 ret;
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__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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return ret;
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}
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#define readl readl
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static inline u32 readl(const volatile void __iomem *addr)
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{ u32 ret;
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__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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return ret;
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}
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#define readq readq
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#define readq_relaxed readq
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static inline u64 readq(const volatile void __iomem *addr)
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{ u64 ret;
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__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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return ret;
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}
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#define writeb writeb
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static inline void writeb(u8 b, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
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: /* no outputs */
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: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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}
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#define writew writew
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static inline void writew(u16 w, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
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: /* no outputs */
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: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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}
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#define writel writel
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static inline void writel(u32 l, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
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: /* no outputs */
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: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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}
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#define writeq writeq
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#define writeq_relaxed writeq
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static inline void writeq(u64 q, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
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: /* no outputs */
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: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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}
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#define inb inb
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static inline u8 inb(unsigned long addr)
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{
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return readb((volatile void __iomem *)addr);
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}
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#define inw inw
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static inline u16 inw(unsigned long addr)
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{
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return readw((volatile void __iomem *)addr);
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}
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#define inl inl
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static inline u32 inl(unsigned long addr)
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{
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return readl((volatile void __iomem *)addr);
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}
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#define outb outb
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static inline void outb(u8 b, unsigned long addr)
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{
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writeb(b, (volatile void __iomem *)addr);
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}
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#define outw outw
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static inline void outw(u16 w, unsigned long addr)
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{
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writew(w, (volatile void __iomem *)addr);
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}
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#define outl outl
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static inline void outl(u32 l, unsigned long addr)
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{
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writel(l, (volatile void __iomem *)addr);
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}
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#define inb_p(__addr) inb(__addr)
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#define outb_p(__b, __addr) outb(__b, __addr)
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#define inw_p(__addr) inw(__addr)
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#define outw_p(__w, __addr) outw(__w, __addr)
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#define inl_p(__addr) inl(__addr)
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#define outl_p(__l, __addr) outl(__l, __addr)
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void outsb(unsigned long, const void *, unsigned long);
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void outsw(unsigned long, const void *, unsigned long);
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void outsl(unsigned long, const void *, unsigned long);
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void insb(unsigned long, void *, unsigned long);
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void insw(unsigned long, void *, unsigned long);
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void insl(unsigned long, void *, unsigned long);
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static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
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{
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insb((unsigned long __force)port, buf, count);
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}
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static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
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{
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insw((unsigned long __force)port, buf, count);
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}
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static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
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{
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insl((unsigned long __force)port, buf, count);
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}
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static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
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{
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outsb((unsigned long __force)port, buf, count);
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}
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static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
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{
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outsw((unsigned long __force)port, buf, count);
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}
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static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
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{
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outsl((unsigned long __force)port, buf, count);
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}
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/* Valid I/O Space regions are anywhere, because each PCI bus supported
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* can live in an arbitrary area of the physical address range.
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*/
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#define IO_SPACE_LIMIT 0xffffffffffffffffUL
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/* Now, SBUS variants, only difference from PCI is that we do
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* not use little-endian ASIs.
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*/
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static inline u8 sbus_readb(const volatile void __iomem *addr)
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{
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return __raw_readb(addr);
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}
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static inline u16 sbus_readw(const volatile void __iomem *addr)
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{
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return __raw_readw(addr);
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}
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static inline u32 sbus_readl(const volatile void __iomem *addr)
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{
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return __raw_readl(addr);
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}
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static inline u64 sbus_readq(const volatile void __iomem *addr)
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{
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return __raw_readq(addr);
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}
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static inline void sbus_writeb(u8 b, volatile void __iomem *addr)
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{
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__raw_writeb(b, addr);
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}
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static inline void sbus_writew(u16 w, volatile void __iomem *addr)
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{
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__raw_writew(w, addr);
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}
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static inline void sbus_writel(u32 l, volatile void __iomem *addr)
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{
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__raw_writel(l, addr);
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}
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static inline void sbus_writeq(u64 q, volatile void __iomem *addr)
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{
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__raw_writeq(q, addr);
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}
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static inline void sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
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{
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while(n--) {
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sbus_writeb(c, dst);
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dst++;
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}
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}
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static inline void memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
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{
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volatile void __iomem *d = dst;
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while (n--) {
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writeb(c, d);
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d++;
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}
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}
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static inline void sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
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__kernel_size_t n)
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{
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char *d = dst;
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while (n--) {
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char tmp = sbus_readb(src);
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*d++ = tmp;
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src++;
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}
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}
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static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
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__kernel_size_t n)
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{
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char *d = dst;
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while (n--) {
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char tmp = readb(src);
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*d++ = tmp;
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src++;
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}
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}
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static inline void sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
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__kernel_size_t n)
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{
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const char *s = src;
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volatile void __iomem *d = dst;
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while (n--) {
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char tmp = *s++;
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sbus_writeb(tmp, d);
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d++;
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}
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}
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static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
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__kernel_size_t n)
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{
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const char *s = src;
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volatile void __iomem *d = dst;
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while (n--) {
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char tmp = *s++;
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writeb(tmp, d);
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d++;
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}
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}
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#define mmiowb()
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#ifdef __KERNEL__
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/* On sparc64 we have the whole physical IO address space accessible
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* using physically addressed loads and stores, so this does nothing.
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*/
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static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
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{
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return (void __iomem *)offset;
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}
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#define ioremap_nocache(X,Y) ioremap((X),(Y))
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#define ioremap_wc(X,Y) ioremap((X),(Y))
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static inline void iounmap(volatile void __iomem *addr)
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{
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}
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#define ioread8(X) readb(X)
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#define ioread16(X) readw(X)
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#define ioread16be(X) __raw_readw(X)
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#define ioread32(X) readl(X)
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#define ioread32be(X) __raw_readl(X)
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#define iowrite8(val,X) writeb(val,X)
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#define iowrite16(val,X) writew(val,X)
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#define iowrite16be(val,X) __raw_writew(val,X)
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#define iowrite32(val,X) writel(val,X)
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#define iowrite32be(val,X) __raw_writel(val,X)
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/* Create a virtual mapping cookie for an IO port range */
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void __iomem *ioport_map(unsigned long port, unsigned int nr);
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void ioport_unmap(void __iomem *);
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/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
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struct pci_dev;
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void pci_iounmap(struct pci_dev *dev, void __iomem *);
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static inline int sbus_can_dma_64bit(void)
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{
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return 1;
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}
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static inline int sbus_can_burst64(void)
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{
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return 1;
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}
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struct device;
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void sbus_set_sbus64(struct device *, int);
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif
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#endif /* !(__SPARC64_IO_H) */
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