mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 08:06:44 +07:00
7937c6c57e
.recalc_rate callback for the fractional PLL doesn't take operating mode into account when calculating PLL rate. This results in the incorrect PLL rates when PLL is operating in integer mode. Operating mode of fractional PLL is based on the value of the fractional divider. Currently it assumes that the PLL will always be configured in fractional mode which may not be the case. This may result in the wrong output frequency. Also vco was calculated based on the current operating mode which makes no sense because .set_rate is setting operating mode. Instead, vco should be calculated using PLL settings that are about to be set. Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver") Cc: <stable@vger.kernel.org> # 4.1 Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Zdenko Pulitika <zdenko.pulitika@imgtec.com> Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
514 lines
14 KiB
C
514 lines
14 KiB
C
/*
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* Copyright (C) 2014 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/printk.h>
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#include <linux/slab.h>
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#include "clk.h"
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#define PLL_STATUS 0x0
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#define PLL_STATUS_LOCK BIT(0)
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#define PLL_CTRL1 0x4
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#define PLL_CTRL1_REFDIV_SHIFT 0
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#define PLL_CTRL1_REFDIV_MASK 0x3f
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#define PLL_CTRL1_FBDIV_SHIFT 6
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#define PLL_CTRL1_FBDIV_MASK 0xfff
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#define PLL_INT_CTRL1_POSTDIV1_SHIFT 18
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#define PLL_INT_CTRL1_POSTDIV1_MASK 0x7
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#define PLL_INT_CTRL1_POSTDIV2_SHIFT 21
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#define PLL_INT_CTRL1_POSTDIV2_MASK 0x7
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#define PLL_INT_CTRL1_PD BIT(24)
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#define PLL_INT_CTRL1_DSMPD BIT(25)
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#define PLL_INT_CTRL1_FOUTPOSTDIVPD BIT(26)
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#define PLL_INT_CTRL1_FOUTVCOPD BIT(27)
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#define PLL_CTRL2 0x8
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#define PLL_FRAC_CTRL2_FRAC_SHIFT 0
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#define PLL_FRAC_CTRL2_FRAC_MASK 0xffffff
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#define PLL_FRAC_CTRL2_POSTDIV1_SHIFT 24
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#define PLL_FRAC_CTRL2_POSTDIV1_MASK 0x7
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#define PLL_FRAC_CTRL2_POSTDIV2_SHIFT 27
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#define PLL_FRAC_CTRL2_POSTDIV2_MASK 0x7
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#define PLL_INT_CTRL2_BYPASS BIT(28)
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#define PLL_CTRL3 0xc
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#define PLL_FRAC_CTRL3_PD BIT(0)
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#define PLL_FRAC_CTRL3_DACPD BIT(1)
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#define PLL_FRAC_CTRL3_DSMPD BIT(2)
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#define PLL_FRAC_CTRL3_FOUTPOSTDIVPD BIT(3)
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#define PLL_FRAC_CTRL3_FOUT4PHASEPD BIT(4)
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#define PLL_FRAC_CTRL3_FOUTVCOPD BIT(5)
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#define PLL_CTRL4 0x10
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#define PLL_FRAC_CTRL4_BYPASS BIT(28)
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#define MIN_PFD 9600000UL
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#define MIN_VCO_LA 400000000UL
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#define MAX_VCO_LA 1600000000UL
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#define MIN_VCO_FRAC_INT 600000000UL
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#define MAX_VCO_FRAC_INT 1600000000UL
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#define MIN_VCO_FRAC_FRAC 600000000UL
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#define MAX_VCO_FRAC_FRAC 2400000000UL
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#define MIN_OUTPUT_LA 8000000UL
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#define MAX_OUTPUT_LA 1600000000UL
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#define MIN_OUTPUT_FRAC 12000000UL
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#define MAX_OUTPUT_FRAC 1600000000UL
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/* Fractional PLL operating modes */
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enum pll_mode {
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PLL_MODE_FRAC,
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PLL_MODE_INT,
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};
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struct pistachio_clk_pll {
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struct clk_hw hw;
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void __iomem *base;
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struct pistachio_pll_rate_table *rates;
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unsigned int nr_rates;
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};
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static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg)
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{
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return readl(pll->base + reg);
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}
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static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg)
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{
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writel(val, pll->base + reg);
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}
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static inline void pll_lock(struct pistachio_clk_pll *pll)
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{
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while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))
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cpu_relax();
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}
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static inline u64 do_div_round_closest(u64 dividend, u64 divisor)
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{
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dividend += divisor / 2;
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return div64_u64(dividend, divisor);
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}
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static inline struct pistachio_clk_pll *to_pistachio_pll(struct clk_hw *hw)
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{
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return container_of(hw, struct pistachio_clk_pll, hw);
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}
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static inline enum pll_mode pll_frac_get_mode(struct clk_hw *hw)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u32 val;
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val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD;
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return val ? PLL_MODE_INT : PLL_MODE_FRAC;
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}
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static inline void pll_frac_set_mode(struct clk_hw *hw, enum pll_mode mode)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u32 val;
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val = pll_readl(pll, PLL_CTRL3);
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if (mode == PLL_MODE_INT)
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val |= PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_DACPD;
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else
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val &= ~(PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_DACPD);
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pll_writel(pll, val, PLL_CTRL3);
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}
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static struct pistachio_pll_rate_table *
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pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref,
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unsigned long fout)
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{
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unsigned int i;
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for (i = 0; i < pll->nr_rates; i++) {
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if (pll->rates[i].fref == fref && pll->rates[i].fout == fout)
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return &pll->rates[i];
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}
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return NULL;
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}
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static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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unsigned int i;
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for (i = 0; i < pll->nr_rates; i++) {
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if (i > 0 && pll->rates[i].fref == *parent_rate &&
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pll->rates[i].fout <= rate)
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return pll->rates[i - 1].fout;
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}
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return pll->rates[0].fout;
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}
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static int pll_gf40lp_frac_enable(struct clk_hw *hw)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u32 val;
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val = pll_readl(pll, PLL_CTRL3);
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val &= ~(PLL_FRAC_CTRL3_PD | PLL_FRAC_CTRL3_FOUTPOSTDIVPD |
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PLL_FRAC_CTRL3_FOUT4PHASEPD | PLL_FRAC_CTRL3_FOUTVCOPD);
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pll_writel(pll, val, PLL_CTRL3);
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val = pll_readl(pll, PLL_CTRL4);
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val &= ~PLL_FRAC_CTRL4_BYPASS;
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pll_writel(pll, val, PLL_CTRL4);
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pll_lock(pll);
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return 0;
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}
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static void pll_gf40lp_frac_disable(struct clk_hw *hw)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u32 val;
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val = pll_readl(pll, PLL_CTRL3);
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val |= PLL_FRAC_CTRL3_PD;
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pll_writel(pll, val, PLL_CTRL3);
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}
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static int pll_gf40lp_frac_is_enabled(struct clk_hw *hw)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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return !(pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_PD);
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}
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static int pll_gf40lp_frac_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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struct pistachio_pll_rate_table *params;
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int enabled = pll_gf40lp_frac_is_enabled(hw);
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u64 val, vco, old_postdiv1, old_postdiv2;
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const char *name = clk_hw_get_name(hw);
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if (rate < MIN_OUTPUT_FRAC || rate > MAX_OUTPUT_FRAC)
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return -EINVAL;
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params = pll_get_params(pll, parent_rate, rate);
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if (!params || !params->refdiv)
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return -EINVAL;
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/* calculate vco */
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vco = params->fref;
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vco *= (params->fbdiv << 24) + params->frac;
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vco = div64_u64(vco, params->refdiv << 24);
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if (vco < MIN_VCO_FRAC_FRAC || vco > MAX_VCO_FRAC_FRAC)
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pr_warn("%s: VCO %llu is out of range %lu..%lu\n", name, vco,
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MIN_VCO_FRAC_FRAC, MAX_VCO_FRAC_FRAC);
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val = div64_u64(params->fref, params->refdiv);
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if (val < MIN_PFD)
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pr_warn("%s: PFD %llu is too low (min %lu)\n",
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name, val, MIN_PFD);
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if (val > vco / 16)
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pr_warn("%s: PFD %llu is too high (max %llu)\n",
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name, val, vco / 16);
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val = pll_readl(pll, PLL_CTRL1);
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val &= ~((PLL_CTRL1_REFDIV_MASK << PLL_CTRL1_REFDIV_SHIFT) |
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(PLL_CTRL1_FBDIV_MASK << PLL_CTRL1_FBDIV_SHIFT));
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val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) |
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(params->fbdiv << PLL_CTRL1_FBDIV_SHIFT);
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pll_writel(pll, val, PLL_CTRL1);
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val = pll_readl(pll, PLL_CTRL2);
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old_postdiv1 = (val >> PLL_FRAC_CTRL2_POSTDIV1_SHIFT) &
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PLL_FRAC_CTRL2_POSTDIV1_MASK;
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old_postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) &
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PLL_FRAC_CTRL2_POSTDIV2_MASK;
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if (enabled &&
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(params->postdiv1 != old_postdiv1 ||
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params->postdiv2 != old_postdiv2))
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pr_warn("%s: changing postdiv while PLL is enabled\n", name);
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if (params->postdiv2 > params->postdiv1)
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pr_warn("%s: postdiv2 should not exceed postdiv1\n", name);
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val &= ~((PLL_FRAC_CTRL2_FRAC_MASK << PLL_FRAC_CTRL2_FRAC_SHIFT) |
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(PLL_FRAC_CTRL2_POSTDIV1_MASK <<
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PLL_FRAC_CTRL2_POSTDIV1_SHIFT) |
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(PLL_FRAC_CTRL2_POSTDIV2_MASK <<
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PLL_FRAC_CTRL2_POSTDIV2_SHIFT));
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val |= (params->frac << PLL_FRAC_CTRL2_FRAC_SHIFT) |
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(params->postdiv1 << PLL_FRAC_CTRL2_POSTDIV1_SHIFT) |
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(params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT);
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pll_writel(pll, val, PLL_CTRL2);
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/* set operating mode */
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if (params->frac)
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pll_frac_set_mode(hw, PLL_MODE_FRAC);
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else
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pll_frac_set_mode(hw, PLL_MODE_INT);
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if (enabled)
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pll_lock(pll);
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return 0;
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}
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static unsigned long pll_gf40lp_frac_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate;
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val = pll_readl(pll, PLL_CTRL1);
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prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK;
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fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK;
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val = pll_readl(pll, PLL_CTRL2);
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postdiv1 = (val >> PLL_FRAC_CTRL2_POSTDIV1_SHIFT) &
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PLL_FRAC_CTRL2_POSTDIV1_MASK;
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postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) &
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PLL_FRAC_CTRL2_POSTDIV2_MASK;
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frac = (val >> PLL_FRAC_CTRL2_FRAC_SHIFT) & PLL_FRAC_CTRL2_FRAC_MASK;
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/* get operating mode (int/frac) and calculate rate accordingly */
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rate = parent_rate;
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if (pll_frac_get_mode(hw) == PLL_MODE_FRAC)
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rate *= (fbdiv << 24) + frac;
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else
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rate *= (fbdiv << 24);
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rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24);
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return rate;
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}
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static struct clk_ops pll_gf40lp_frac_ops = {
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.enable = pll_gf40lp_frac_enable,
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.disable = pll_gf40lp_frac_disable,
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.is_enabled = pll_gf40lp_frac_is_enabled,
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.recalc_rate = pll_gf40lp_frac_recalc_rate,
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.round_rate = pll_round_rate,
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.set_rate = pll_gf40lp_frac_set_rate,
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};
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static struct clk_ops pll_gf40lp_frac_fixed_ops = {
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.enable = pll_gf40lp_frac_enable,
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.disable = pll_gf40lp_frac_disable,
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.is_enabled = pll_gf40lp_frac_is_enabled,
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.recalc_rate = pll_gf40lp_frac_recalc_rate,
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};
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static int pll_gf40lp_laint_enable(struct clk_hw *hw)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u32 val;
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val = pll_readl(pll, PLL_CTRL1);
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val &= ~(PLL_INT_CTRL1_PD |
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PLL_INT_CTRL1_FOUTPOSTDIVPD | PLL_INT_CTRL1_FOUTVCOPD);
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pll_writel(pll, val, PLL_CTRL1);
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val = pll_readl(pll, PLL_CTRL2);
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val &= ~PLL_INT_CTRL2_BYPASS;
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pll_writel(pll, val, PLL_CTRL2);
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pll_lock(pll);
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return 0;
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}
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static void pll_gf40lp_laint_disable(struct clk_hw *hw)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u32 val;
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val = pll_readl(pll, PLL_CTRL1);
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val |= PLL_INT_CTRL1_PD;
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pll_writel(pll, val, PLL_CTRL1);
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}
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static int pll_gf40lp_laint_is_enabled(struct clk_hw *hw)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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return !(pll_readl(pll, PLL_CTRL1) & PLL_INT_CTRL1_PD);
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}
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static int pll_gf40lp_laint_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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struct pistachio_pll_rate_table *params;
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int enabled = pll_gf40lp_laint_is_enabled(hw);
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u32 val, vco, old_postdiv1, old_postdiv2;
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const char *name = clk_hw_get_name(hw);
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if (rate < MIN_OUTPUT_LA || rate > MAX_OUTPUT_LA)
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return -EINVAL;
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params = pll_get_params(pll, parent_rate, rate);
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if (!params || !params->refdiv)
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return -EINVAL;
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vco = div_u64(params->fref * params->fbdiv, params->refdiv);
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if (vco < MIN_VCO_LA || vco > MAX_VCO_LA)
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pr_warn("%s: VCO %u is out of range %lu..%lu\n", name, vco,
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MIN_VCO_LA, MAX_VCO_LA);
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val = div_u64(params->fref, params->refdiv);
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if (val < MIN_PFD)
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pr_warn("%s: PFD %u is too low (min %lu)\n",
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name, val, MIN_PFD);
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if (val > vco / 16)
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pr_warn("%s: PFD %u is too high (max %u)\n",
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name, val, vco / 16);
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val = pll_readl(pll, PLL_CTRL1);
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old_postdiv1 = (val >> PLL_INT_CTRL1_POSTDIV1_SHIFT) &
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PLL_INT_CTRL1_POSTDIV1_MASK;
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old_postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) &
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PLL_INT_CTRL1_POSTDIV2_MASK;
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if (enabled &&
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(params->postdiv1 != old_postdiv1 ||
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params->postdiv2 != old_postdiv2))
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pr_warn("%s: changing postdiv while PLL is enabled\n", name);
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if (params->postdiv2 > params->postdiv1)
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pr_warn("%s: postdiv2 should not exceed postdiv1\n", name);
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val &= ~((PLL_CTRL1_REFDIV_MASK << PLL_CTRL1_REFDIV_SHIFT) |
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(PLL_CTRL1_FBDIV_MASK << PLL_CTRL1_FBDIV_SHIFT) |
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(PLL_INT_CTRL1_POSTDIV1_MASK << PLL_INT_CTRL1_POSTDIV1_SHIFT) |
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(PLL_INT_CTRL1_POSTDIV2_MASK << PLL_INT_CTRL1_POSTDIV2_SHIFT));
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val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) |
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(params->fbdiv << PLL_CTRL1_FBDIV_SHIFT) |
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(params->postdiv1 << PLL_INT_CTRL1_POSTDIV1_SHIFT) |
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(params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT);
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pll_writel(pll, val, PLL_CTRL1);
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if (enabled)
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pll_lock(pll);
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return 0;
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}
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static unsigned long pll_gf40lp_laint_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u32 val, prediv, fbdiv, postdiv1, postdiv2;
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u64 rate = parent_rate;
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val = pll_readl(pll, PLL_CTRL1);
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prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK;
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fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK;
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postdiv1 = (val >> PLL_INT_CTRL1_POSTDIV1_SHIFT) &
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PLL_INT_CTRL1_POSTDIV1_MASK;
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postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) &
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PLL_INT_CTRL1_POSTDIV2_MASK;
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rate *= fbdiv;
|
|
rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2);
|
|
|
|
return rate;
|
|
}
|
|
|
|
static struct clk_ops pll_gf40lp_laint_ops = {
|
|
.enable = pll_gf40lp_laint_enable,
|
|
.disable = pll_gf40lp_laint_disable,
|
|
.is_enabled = pll_gf40lp_laint_is_enabled,
|
|
.recalc_rate = pll_gf40lp_laint_recalc_rate,
|
|
.round_rate = pll_round_rate,
|
|
.set_rate = pll_gf40lp_laint_set_rate,
|
|
};
|
|
|
|
static struct clk_ops pll_gf40lp_laint_fixed_ops = {
|
|
.enable = pll_gf40lp_laint_enable,
|
|
.disable = pll_gf40lp_laint_disable,
|
|
.is_enabled = pll_gf40lp_laint_is_enabled,
|
|
.recalc_rate = pll_gf40lp_laint_recalc_rate,
|
|
};
|
|
|
|
static struct clk *pll_register(const char *name, const char *parent_name,
|
|
unsigned long flags, void __iomem *base,
|
|
enum pistachio_pll_type type,
|
|
struct pistachio_pll_rate_table *rates,
|
|
unsigned int nr_rates)
|
|
{
|
|
struct pistachio_clk_pll *pll;
|
|
struct clk_init_data init;
|
|
struct clk *clk;
|
|
|
|
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
|
if (!pll)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
init.name = name;
|
|
init.flags = flags | CLK_GET_RATE_NOCACHE;
|
|
init.parent_names = &parent_name;
|
|
init.num_parents = 1;
|
|
|
|
switch (type) {
|
|
case PLL_GF40LP_FRAC:
|
|
if (rates)
|
|
init.ops = &pll_gf40lp_frac_ops;
|
|
else
|
|
init.ops = &pll_gf40lp_frac_fixed_ops;
|
|
break;
|
|
case PLL_GF40LP_LAINT:
|
|
if (rates)
|
|
init.ops = &pll_gf40lp_laint_ops;
|
|
else
|
|
init.ops = &pll_gf40lp_laint_fixed_ops;
|
|
break;
|
|
default:
|
|
pr_err("Unrecognized PLL type %u\n", type);
|
|
kfree(pll);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
pll->hw.init = &init;
|
|
pll->base = base;
|
|
pll->rates = rates;
|
|
pll->nr_rates = nr_rates;
|
|
|
|
clk = clk_register(NULL, &pll->hw);
|
|
if (IS_ERR(clk))
|
|
kfree(pll);
|
|
|
|
return clk;
|
|
}
|
|
|
|
void pistachio_clk_register_pll(struct pistachio_clk_provider *p,
|
|
struct pistachio_pll *pll,
|
|
unsigned int num)
|
|
{
|
|
struct clk *clk;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < num; i++) {
|
|
clk = pll_register(pll[i].name, pll[i].parent,
|
|
0, p->base + pll[i].reg_base,
|
|
pll[i].type, pll[i].rates,
|
|
pll[i].nr_rates);
|
|
p->clk_data.clks[pll[i].id] = clk;
|
|
}
|
|
}
|