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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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116f4a640b
The 82574 specification update errata 12 states that interrupts may be missed if ICR is read while INT_ASSERTED is not set. Avoid that problem by setting all bits related to events that can trigger the Other interrupt in IMS. The Other interrupt is raised for such events regardless of whether or not they are set in IMS. However, only when they are set is the INT_ASSERTED bit also set in ICR. By doing this, we ensure that INT_ASSERTED is always set when we read ICR in e1000_msix_other() and steer clear of the errata. This also ensures that ICR will automatically be cleared on read, therefore we no longer need to clear bits explicitly. Signed-off-by: Benjamin Poirier <bpoirier@suse.com> Acked-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> |
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| .. | ||
| 80003es2lan.c | ||
| 80003es2lan.h | ||
| 82571.c | ||
| 82571.h | ||
| defines.h | ||
| e1000.h | ||
| ethtool.c | ||
| hw.h | ||
| ich8lan.c | ||
| ich8lan.h | ||
| mac.c | ||
| mac.h | ||
| Makefile | ||
| manage.c | ||
| manage.h | ||
| netdev.c | ||
| nvm.c | ||
| nvm.h | ||
| param.c | ||
| phy.c | ||
| phy.h | ||
| ptp.c | ||
| regs.h | ||