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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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179cbdb874
MU4_INT correct number is 180, while 179 is for MU3_INT.
Fixes: 3d91ba65fe ("arm64: dts: imx: add imx8qxp support")
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
447 lines
12 KiB
Plaintext
447 lines
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/clock/imx8-clock.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/pads-imx8qxp.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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serial0 = &adma_lpuart0;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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/* We have 1 clusters with 4 Cortex-A35 cores */
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A35_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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};
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A35_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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};
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A35_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x2>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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};
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A35_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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};
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A35_L2: l2-cache0 {
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compatible = "cache";
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};
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};
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gic: interrupt-controller@51a00000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
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<0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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scu {
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compatible = "fsl,imx-scu";
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mbox-names = "tx0", "tx1", "tx2", "tx3",
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"rx0", "rx1", "rx2", "rx3";
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mboxes = <&lsio_mu1 0 0
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&lsio_mu1 0 1
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&lsio_mu1 0 2
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&lsio_mu1 0 3
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&lsio_mu1 1 0
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&lsio_mu1 1 1
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&lsio_mu1 1 2
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&lsio_mu1 1 3>;
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clk: clock-controller {
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compatible = "fsl,imx8qxp-clk";
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#clock-cells = <1>;
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clocks = <&xtal32k &xtal24m>;
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clock-names = "xtal_32KHz", "xtal_24Mhz";
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};
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iomuxc: pinctrl {
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compatible = "fsl,imx8qxp-iomuxc";
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};
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pd: imx8qx-pd {
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compatible = "fsl,imx8qxp-scu-pd";
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#power-domain-cells = <1>;
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};
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rtc: rtc {
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compatible = "fsl,imx8qxp-sc-rtc";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
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};
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xtal32k: clock-xtal32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "xtal_32KHz";
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};
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xtal24m: clock-xtal24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "xtal_24MHz";
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};
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adma_subsys: bus@59000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x59000000 0x0 0x59000000 0x2000000>;
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adma_lpcg: clock-controller@59000000 {
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compatible = "fsl,imx8qxp-lpcg-adma";
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reg = <0x59000000 0x2000000>;
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#clock-cells = <1>;
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};
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adma_lpuart0: serial@5a060000 {
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
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reg = <0x5a060000 0x1000>;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
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clock-names = "ipg";
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power-domains = <&pd IMX_SC_R_UART_0>;
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status = "disabled";
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};
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adma_i2c0: i2c@5a800000 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x5a800000 0x4000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
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clock-names = "per";
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assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_I2C_0>;
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status = "disabled";
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};
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adma_i2c1: i2c@5a810000 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x5a810000 0x4000>;
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
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clock-names = "per";
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assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_I2C_1>;
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status = "disabled";
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};
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adma_i2c2: i2c@5a820000 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x5a820000 0x4000>;
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
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clock-names = "per";
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assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_I2C_2>;
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status = "disabled";
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};
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adma_i2c3: i2c@5a830000 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x5a830000 0x4000>;
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
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clock-names = "per";
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assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_I2C_3>;
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status = "disabled";
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};
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};
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conn_subsys: bus@5b000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
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conn_lpcg: clock-controller@5b200000 {
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compatible = "fsl,imx8qxp-lpcg-conn";
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reg = <0x5b200000 0xb0000>;
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#clock-cells = <1>;
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};
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usdhc1: mmc@5b010000 {
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compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x5b010000 0x10000>;
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clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
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<&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
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<&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
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clock-names = "ipg", "per", "ahb";
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assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
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assigned-clock-rates = <200000000>;
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power-domains = <&pd IMX_SC_R_SDHC_0>;
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status = "disabled";
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};
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usdhc2: mmc@5b020000 {
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compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x5b020000 0x10000>;
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clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
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<&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
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<&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
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clock-names = "ipg", "per", "ahb";
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assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
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assigned-clock-rates = <200000000>;
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power-domains = <&pd IMX_SC_R_SDHC_1>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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status = "disabled";
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};
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usdhc3: mmc@5b030000 {
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compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x5b030000 0x10000>;
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clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
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<&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
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<&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
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clock-names = "ipg", "per", "ahb";
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assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
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assigned-clock-rates = <200000000>;
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power-domains = <&pd IMX_SC_R_SDHC_2>;
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status = "disabled";
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};
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fec1: ethernet@5b040000 {
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compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
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reg = <0x5b040000 0x10000>;
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interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
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<&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
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<&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
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<&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
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clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
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fsl,num-tx-queues=<3>;
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fsl,num-rx-queues=<3>;
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power-domains = <&pd IMX_SC_R_ENET_0>;
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status = "disabled";
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};
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fec2: ethernet@5b050000 {
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compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
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reg = <0x5b050000 0x10000>;
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interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
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<&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
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<&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
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<&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
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clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
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fsl,num-tx-queues=<3>;
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fsl,num-rx-queues=<3>;
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power-domains = <&pd IMX_SC_R_ENET_1>;
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status = "disabled";
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};
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};
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lsio_subsys: bus@5d000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
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lsio_lpcg: clock-controller@5d400000 {
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compatible = "fsl,imx8qxp-lpcg-lsio";
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reg = <0x5d400000 0x400000>;
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#clock-cells = <1>;
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};
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lsio_mu0: mailbox@5d1b0000 {
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compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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reg = <0x5d1b0000 0x10000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <0>;
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status = "disabled";
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};
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lsio_mu1: mailbox@5d1c0000 {
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compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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reg = <0x5d1c0000 0x10000>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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};
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lsio_mu3: mailbox@5d1e0000 {
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compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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reg = <0x5d1e0000 0x10000>;
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interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <0>;
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status = "disabled";
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};
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lsio_mu4: mailbox@5d1f0000 {
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compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
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reg = <0x5d1f0000 0x10000>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <0>;
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status = "disabled";
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};
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lsio_gpio0: gpio@5d080000 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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reg = <0x5d080000 0x10000>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_0>;
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};
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lsio_gpio1: gpio@5d090000 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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reg = <0x5d090000 0x10000>;
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_1>;
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};
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lsio_gpio2: gpio@5d0a0000 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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reg = <0x5d0a0000 0x10000>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_2>;
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};
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lsio_gpio3: gpio@5d0b0000 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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reg = <0x5d0b0000 0x10000>;
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interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_3>;
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};
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lsio_gpio4: gpio@5d0c0000 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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reg = <0x5d0c0000 0x10000>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_4>;
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};
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lsio_gpio5: gpio@5d0d0000 {
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
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reg = <0x5d0d0000 0x10000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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power-domains = <&pd IMX_SC_R_GPIO_5>;
|
|
};
|
|
|
|
lsio_gpio6: gpio@5d0e0000 {
|
|
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
|
|
reg = <0x5d0e0000 0x10000>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
power-domains = <&pd IMX_SC_R_GPIO_6>;
|
|
};
|
|
|
|
lsio_gpio7: gpio@5d0f0000 {
|
|
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
|
|
reg = <0x5d0f0000 0x10000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
power-domains = <&pd IMX_SC_R_GPIO_7>;
|
|
};
|
|
};
|
|
};
|