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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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729303191e
The DB8500v2 and DB5500 has a fifth version of the "PL023" and PL180 blocks. However the ASIC engineers have forgot to bump the revision in the PrimeCell peripheral ID registers. Since the platform is aware of the actual silicon revision we need to hard-code the periphid from the platform, bumping the subrevision field to 1. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
219 lines
5.7 KiB
C
219 lines
5.7 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* Author: Hanumath Prasad <hanumath.prasad@stericsson.com>
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/kernel.h>
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#include <linux/gpio.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/mmci.h>
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#include <linux/mmc/host.h>
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#include <linux/platform_device.h>
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#include <asm/mach-types.h>
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#include <plat/ste_dma40.h>
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#include <mach/devices.h>
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#include <mach/hardware.h>
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#include "devices-db8500.h"
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#include "board-mop500.h"
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#include "ste-dma40-db8500.h"
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/*
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* SDI 0 (MicroSD slot)
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*/
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/* MMCIPOWER bits */
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#define MCI_DATA2DIREN (1 << 2)
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#define MCI_CMDDIREN (1 << 3)
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#define MCI_DATA0DIREN (1 << 4)
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#define MCI_DATA31DIREN (1 << 5)
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#define MCI_FBCLKEN (1 << 7)
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static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
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unsigned char power_mode)
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{
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if (power_mode == MMC_POWER_UP)
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gpio_set_value_cansleep(GPIO_SDMMC_EN, 1);
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else if (power_mode == MMC_POWER_OFF)
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gpio_set_value_cansleep(GPIO_SDMMC_EN, 0);
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return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN |
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MCI_DATA2DIREN | MCI_DATA31DIREN;
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}
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#ifdef CONFIG_STE_DMA40
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struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
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.mode = STEDMA40_MODE_LOGICAL,
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.dir = STEDMA40_PERIPH_TO_MEM,
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.src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
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.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
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.src_info.data_width = STEDMA40_WORD_WIDTH,
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.dst_info.data_width = STEDMA40_WORD_WIDTH,
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};
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static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
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.mode = STEDMA40_MODE_LOGICAL,
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.dir = STEDMA40_MEM_TO_PERIPH,
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.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
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.dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
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.src_info.data_width = STEDMA40_WORD_WIDTH,
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.dst_info.data_width = STEDMA40_WORD_WIDTH,
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};
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#endif
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static struct mmci_platform_data mop500_sdi0_data = {
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.vdd_handler = mop500_sdi0_vdd_handler,
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.ocr_mask = MMC_VDD_29_30,
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.f_max = 100000000,
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.capabilities = MMC_CAP_4_BIT_DATA,
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.gpio_wp = -1,
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#ifdef CONFIG_STE_DMA40
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.dma_filter = stedma40_filter,
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.dma_rx_param = &mop500_sdi0_dma_cfg_rx,
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.dma_tx_param = &mop500_sdi0_dma_cfg_tx,
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#endif
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};
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/* GPIO pins used by the sdi0 level shifter */
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static int sdi0_en = -1;
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static int sdi0_vsel = -1;
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static void sdi0_configure(void)
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{
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int ret;
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ret = gpio_request(sdi0_en, "level shifter enable");
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if (!ret)
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ret = gpio_request(sdi0_vsel,
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"level shifter 1v8-3v select");
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if (ret) {
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pr_warning("unable to config sdi0 gpios for level shifter.\n");
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return;
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}
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/* Select the default 2.9V and enable level shifter */
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gpio_direction_output(sdi0_vsel, 0);
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gpio_direction_output(sdi0_en, 1);
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/* Add the device, force v2 to subrevision 1 */
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if (cpu_is_u8500v2())
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db8500_add_sdi0(&mop500_sdi0_data, 0x10480180);
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else
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db8500_add_sdi0(&mop500_sdi0_data, 0);
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}
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void mop500_sdi_tc35892_init(void)
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{
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mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
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sdi0_en = GPIO_SDMMC_EN;
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sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
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sdi0_configure();
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}
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/*
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* SDI 2 (POP eMMC, not on DB8500ed)
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*/
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#ifdef CONFIG_STE_DMA40
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struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
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.mode = STEDMA40_MODE_LOGICAL,
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.dir = STEDMA40_PERIPH_TO_MEM,
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.src_dev_type = DB8500_DMA_DEV28_SD_MM2_RX,
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.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
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.src_info.data_width = STEDMA40_WORD_WIDTH,
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.dst_info.data_width = STEDMA40_WORD_WIDTH,
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};
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static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
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.mode = STEDMA40_MODE_LOGICAL,
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.dir = STEDMA40_MEM_TO_PERIPH,
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.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
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.dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
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.src_info.data_width = STEDMA40_WORD_WIDTH,
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.dst_info.data_width = STEDMA40_WORD_WIDTH,
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};
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#endif
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static struct mmci_platform_data mop500_sdi2_data = {
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.ocr_mask = MMC_VDD_165_195,
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.f_max = 100000000,
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.capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
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.gpio_cd = -1,
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.gpio_wp = -1,
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#ifdef CONFIG_STE_DMA40
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.dma_filter = stedma40_filter,
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.dma_rx_param = &mop500_sdi2_dma_cfg_rx,
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.dma_tx_param = &mop500_sdi2_dma_cfg_tx,
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#endif
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};
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/*
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* SDI 4 (on-board eMMC)
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*/
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#ifdef CONFIG_STE_DMA40
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struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
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.mode = STEDMA40_MODE_LOGICAL,
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.dir = STEDMA40_PERIPH_TO_MEM,
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.src_dev_type = DB8500_DMA_DEV42_SD_MM4_RX,
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.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
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.src_info.data_width = STEDMA40_WORD_WIDTH,
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.dst_info.data_width = STEDMA40_WORD_WIDTH,
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};
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static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
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.mode = STEDMA40_MODE_LOGICAL,
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.dir = STEDMA40_MEM_TO_PERIPH,
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.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
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.dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
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.src_info.data_width = STEDMA40_WORD_WIDTH,
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.dst_info.data_width = STEDMA40_WORD_WIDTH,
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};
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#endif
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static struct mmci_platform_data mop500_sdi4_data = {
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.ocr_mask = MMC_VDD_29_30,
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.f_max = 100000000,
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.capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
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MMC_CAP_MMC_HIGHSPEED,
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.gpio_cd = -1,
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.gpio_wp = -1,
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#ifdef CONFIG_STE_DMA40
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.dma_filter = stedma40_filter,
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.dma_rx_param = &mop500_sdi4_dma_cfg_rx,
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.dma_tx_param = &mop500_sdi4_dma_cfg_tx,
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#endif
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};
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void __init mop500_sdi_init(void)
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{
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u32 periphid = 0;
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/* v2 has a new version of this block that need to be forced */
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if (cpu_is_u8500v2())
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periphid = 0x10480180;
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/* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
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if (!cpu_is_u8500v10())
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mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
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db8500_add_sdi2(&mop500_sdi2_data, periphid);
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/* On-board eMMC */
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db8500_add_sdi4(&mop500_sdi4_data, periphid);
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if (machine_is_hrefv60()) {
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mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
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sdi0_en = HREFV60_SDMMC_EN_GPIO;
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sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
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sdi0_configure();
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}
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/*
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* On boards with the TC35892 GPIO expander, sdi0 will finally
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* be added when the TC35892 initializes and calls
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* mop500_sdi_tc35892_init() above.
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*/
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}
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