mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 07:55:25 +07:00
a10f361d17
This reverts commit1ac159e23c
("drm/i915: Expand subslice mask"), which kills ICL due to GEM_BUG_ON() sanity checks before CI even gets a chance to do anything. The commit exposes an issue in commit1e40d4aea5
("drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads"), which will also need to be addressed. There's a proposed fix [1], but considering the seeming uncertainty with the fix as well as the size of the regressing commit (in this context, the one that actually brings down ICL), this warrants a revert to get ICL working, and gives us time to get all of this right without rushing. Even if this means shooting the messenger. <3>[ 9.426327] intel_sseu_get_subslices:46 GEM_BUG_ON(slice >= sseu->max_slices) <4>[ 9.426355] ------------[ cut here ]------------ <2>[ 9.426357] kernel BUG at drivers/gpu/drm/i915/gt/intel_sseu.c:46! <4>[ 9.426371] invalid opcode: 0000 [#1] PREEMPT SMP NOPTI <4>[ 9.426377] CPU: 1 PID: 364 Comm: systemd-udevd Not tainted 5.2.0-rc2-CI-CI_DRM_6159+ #1 <4>[ 9.426385] Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 SODIMM PD RVP TLC, BIOS ICLSFWR1.R00.3183.A00.1905020411 05/02/2019 <4>[ 9.426444] RIP: 0010:intel_sseu_get_subslices+0x8a/0xe0 [i915] <4>[ 9.426452] Code: d5 76 b7 e0 48 8b 35 9d 24 21 00 49 c7 c0 07 f0 72 a0 b9 2e 00 00 00 48 c7 c2 00 8e 6d a0 48 c7 c7 a5 14 5b a0 e8 36 3c be e0 <0f> 0b 48 c7 c1 80 d5 6f a0 ba 30 00 00 00 48 c7 c6 00 8e 6d a0 48 <4>[ 9.426468] RSP: 0018:ffffc9000037b9c8 EFLAGS: 00010282 <4>[ 9.426475] RAX: 000000000000000f RBX: 0000000000000000 RCX: 0000000000000000 <4>[ 9.426482] RDX: 0000000000000001 RSI: 0000000000000008 RDI: ffff88849e346f98 <4>[ 9.426490] RBP: ffff88848a200000 R08: 0000000000000004 R09: ffff88849d50b000 <4>[ 9.426497] R10: 0000000000000000 R11: ffff88849e346f98 R12: ffff88848a209e78 <4>[ 9.426505] R13: 0000000003000000 R14: ffff88848a20b1a8 R15: 0000000000000000 <4>[ 9.426513] FS: 00007f73d5ae8680(0000) GS:ffff88849fc80000(0000) knlGS:0000000000000000 <4>[ 9.426521] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4>[ 9.426527] CR2: 0000561417b01260 CR3: 0000000494764003 CR4: 0000000000760ee0 <4>[ 9.426535] PKRU: 55555554 <4>[ 9.426538] Call Trace: <4>[ 9.426585] wa_init_mcr+0xd5/0x110 [i915] <4>[ 9.426597] ? lock_acquire+0xa6/0x1c0 <4>[ 9.426645] icl_gt_workarounds_init+0x21/0x1a0 [i915] <4>[ 9.426694] ? i915_driver_load+0xfcf/0x18a0 [i915] <4>[ 9.426739] gt_init_workarounds+0x14c/0x230 [i915] <4>[ 9.426748] ? _raw_spin_unlock_irq+0x24/0x50 <4>[ 9.426789] intel_gt_init_workarounds+0x1b/0x30 [i915] <4>[ 9.426835] i915_driver_load+0xfd7/0x18a0 [i915] <4>[ 9.426843] ? lock_acquire+0xa6/0x1c0 <4>[ 9.426850] ? __pm_runtime_resume+0x4f/0x80 <4>[ 9.426857] ? _raw_spin_unlock_irqrestore+0x4c/0x60 <4>[ 9.426863] ? _raw_spin_unlock_irqrestore+0x4c/0x60 <4>[ 9.426870] ? lockdep_hardirqs_on+0xe3/0x1b0 <4>[ 9.426915] i915_pci_probe+0x29/0xa0 [i915] <4>[ 9.426923] pci_device_probe+0x9e/0x120 <4>[ 9.426930] really_probe+0xea/0x3c0 <4>[ 9.426936] driver_probe_device+0x10b/0x120 <4>[ 9.426942] device_driver_attach+0x4a/0x50 <4>[ 9.426948] __driver_attach+0x97/0x130 <4>[ 9.426954] ? device_driver_attach+0x50/0x50 <4>[ 9.426960] bus_for_each_dev+0x74/0xc0 <4>[ 9.426966] bus_add_driver+0x13f/0x210 <4>[ 9.426971] ? 0xffffffffa083b000 <4>[ 9.426976] driver_register+0x56/0xe0 <4>[ 9.426982] ? 0xffffffffa083b000 <4>[ 9.426987] do_one_initcall+0x58/0x300 <4>[ 9.426994] ? do_init_module+0x1d/0x1f6 <4>[ 9.427001] ? rcu_read_lock_sched_held+0x6f/0x80 <4>[ 9.427007] ? kmem_cache_alloc_trace+0x261/0x290 <4>[ 9.427014] do_init_module+0x56/0x1f6 <4>[ 9.427020] load_module+0x24d1/0x2990 <4>[ 9.427032] ? __se_sys_finit_module+0xd3/0xf0 <4>[ 9.427037] __se_sys_finit_module+0xd3/0xf0 <4>[ 9.427047] do_syscall_64+0x55/0x1c0 <4>[ 9.427053] entry_SYSCALL_64_after_hwframe+0x49/0xbe <4>[ 9.427059] RIP: 0033:0x7f73d5609839 <4>[ 9.427064] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48 <4>[ 9.427082] RSP: 002b:00007ffdf34477b8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 <4>[ 9.427091] RAX: ffffffffffffffda RBX: 00005559fd5d7b40 RCX: 00007f73d5609839 <4>[ 9.427099] RDX: 0000000000000000 RSI: 00007f73d52e8145 RDI: 000000000000000f <4>[ 9.427106] RBP: 00007f73d52e8145 R08: 0000000000000000 R09: 00007ffdf34478d0 <4>[ 9.427114] R10: 000000000000000f R11: 0000000000000246 R12: 0000000000000000 <4>[ 9.427121] R13: 00005559fd5c90f0 R14: 0000000000020000 R15: 00005559fd5d7b40 <4>[ 9.427131] Modules linked in: i915(+) mei_hdcp x86_pkg_temp_thermal coretemp snd_hda_intel crct10dif_pclmul crc32_pclmul snd_hda_codec snd_hwdep e1000e snd_hda_core ghash_clmulni_intel ptp snd_pcm cdc_ether usbnet mii pps_core mei_me mei prime_numbers btusb btrtl btbcm btintel bluetooth ecdh_generic ecc <4>[ 9.427254] ---[ end trace af3eeb543bd66e66 ]--- [1] http://patchwork.freedesktop.org/patch/msgid/20190528200655.11605-1-chris@chris-wilson.co.uk References: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/fi-icl-u2/pstore0-1517155098_Oops_1.log References:1e40d4aea5
("drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads") Fixes:1ac159e23c
("drm/i915: Expand subslice mask") Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Oscar Mateo <oscar.mateo@intel.com> Cc: Stuart Summers <stuart.summers@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Yunwei Zhang <yunwei.zhang@intel.com> Acked-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190529082150.31526-1-jani.nikula@intel.com
348 lines
9.4 KiB
C
348 lines
9.4 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "intel_reset.h"
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#include "i915_drv.h"
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struct hangcheck {
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u64 acthd;
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u32 ring;
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u32 head;
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enum intel_engine_hangcheck_action action;
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unsigned long action_timestamp;
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int deadlock;
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struct intel_instdone instdone;
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bool wedged:1;
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bool stalled:1;
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};
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static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
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{
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u32 tmp = current_instdone | *old_instdone;
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bool unchanged;
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unchanged = tmp == *old_instdone;
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*old_instdone |= tmp;
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return unchanged;
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}
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static bool subunits_stuck(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct intel_instdone instdone;
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struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
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bool stuck;
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int slice;
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int subslice;
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if (engine->id != RCS0)
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return true;
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intel_engine_get_instdone(engine, &instdone);
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/* There might be unstable subunit states even when
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* actual head is not moving. Filter out the unstable ones by
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* accumulating the undone -> done transitions and only
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* consider those as progress.
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*/
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stuck = instdone_unchanged(instdone.instdone,
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&accu_instdone->instdone);
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stuck &= instdone_unchanged(instdone.slice_common,
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&accu_instdone->slice_common);
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for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
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stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
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&accu_instdone->sampler[slice][subslice]);
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stuck &= instdone_unchanged(instdone.row[slice][subslice],
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&accu_instdone->row[slice][subslice]);
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}
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return stuck;
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}
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static enum intel_engine_hangcheck_action
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head_stuck(struct intel_engine_cs *engine, u64 acthd)
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{
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if (acthd != engine->hangcheck.acthd) {
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/* Clear subunit states on head movement */
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memset(&engine->hangcheck.instdone, 0,
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sizeof(engine->hangcheck.instdone));
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return ENGINE_ACTIVE_HEAD;
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}
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if (!subunits_stuck(engine))
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return ENGINE_ACTIVE_SUBUNITS;
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return ENGINE_DEAD;
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}
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static enum intel_engine_hangcheck_action
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engine_stuck(struct intel_engine_cs *engine, u64 acthd)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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enum intel_engine_hangcheck_action ha;
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u32 tmp;
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ha = head_stuck(engine, acthd);
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if (ha != ENGINE_DEAD)
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return ha;
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if (IS_GEN(dev_priv, 2))
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return ENGINE_DEAD;
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/* Is the chip hanging on a WAIT_FOR_EVENT?
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* If so we can simply poke the RB_WAIT bit
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* and break the hang. This should work on
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* all but the second generation chipsets.
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*/
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tmp = ENGINE_READ(engine, RING_CTL);
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if (tmp & RING_WAIT) {
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i915_handle_error(dev_priv, engine->mask, 0,
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"stuck wait on %s", engine->name);
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ENGINE_WRITE(engine, RING_CTL, tmp);
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return ENGINE_WAIT_KICK;
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}
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return ENGINE_DEAD;
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}
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static void hangcheck_load_sample(struct intel_engine_cs *engine,
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struct hangcheck *hc)
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{
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hc->acthd = intel_engine_get_active_head(engine);
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hc->ring = ENGINE_READ(engine, RING_START);
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hc->head = ENGINE_READ(engine, RING_HEAD);
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}
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static void hangcheck_store_sample(struct intel_engine_cs *engine,
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const struct hangcheck *hc)
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{
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engine->hangcheck.acthd = hc->acthd;
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engine->hangcheck.last_ring = hc->ring;
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engine->hangcheck.last_head = hc->head;
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}
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static enum intel_engine_hangcheck_action
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hangcheck_get_action(struct intel_engine_cs *engine,
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const struct hangcheck *hc)
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{
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if (intel_engine_is_idle(engine))
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return ENGINE_IDLE;
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if (engine->hangcheck.last_ring != hc->ring)
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return ENGINE_ACTIVE_SEQNO;
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if (engine->hangcheck.last_head != hc->head)
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return ENGINE_ACTIVE_SEQNO;
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return engine_stuck(engine, hc->acthd);
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}
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static void hangcheck_accumulate_sample(struct intel_engine_cs *engine,
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struct hangcheck *hc)
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{
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unsigned long timeout = I915_ENGINE_DEAD_TIMEOUT;
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hc->action = hangcheck_get_action(engine, hc);
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/* We always increment the progress
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* if the engine is busy and still processing
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* the same request, so that no single request
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* can run indefinitely (such as a chain of
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* batches). The only time we do not increment
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* the hangcheck score on this ring, if this
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* engine is in a legitimate wait for another
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* engine. In that case the waiting engine is a
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* victim and we want to be sure we catch the
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* right culprit. Then every time we do kick
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* the ring, make it as a progress as the seqno
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* advancement might ensure and if not, it
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* will catch the hanging engine.
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*/
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switch (hc->action) {
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case ENGINE_IDLE:
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case ENGINE_ACTIVE_SEQNO:
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/* Clear head and subunit states on seqno movement */
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hc->acthd = 0;
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memset(&engine->hangcheck.instdone, 0,
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sizeof(engine->hangcheck.instdone));
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/* Intentional fall through */
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case ENGINE_WAIT_KICK:
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case ENGINE_WAIT:
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engine->hangcheck.action_timestamp = jiffies;
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break;
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case ENGINE_ACTIVE_HEAD:
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case ENGINE_ACTIVE_SUBUNITS:
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/*
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* Seqno stuck with still active engine gets leeway,
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* in hopes that it is just a long shader.
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*/
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timeout = I915_SEQNO_DEAD_TIMEOUT;
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break;
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case ENGINE_DEAD:
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break;
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default:
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MISSING_CASE(hc->action);
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}
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hc->stalled = time_after(jiffies,
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engine->hangcheck.action_timestamp + timeout);
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hc->wedged = time_after(jiffies,
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engine->hangcheck.action_timestamp +
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I915_ENGINE_WEDGED_TIMEOUT);
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}
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static void hangcheck_declare_hang(struct drm_i915_private *i915,
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unsigned int hung,
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unsigned int stuck)
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{
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struct intel_engine_cs *engine;
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intel_engine_mask_t tmp;
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char msg[80];
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int len;
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/* If some rings hung but others were still busy, only
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* blame the hanging rings in the synopsis.
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*/
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if (stuck != hung)
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hung &= ~stuck;
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len = scnprintf(msg, sizeof(msg),
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"%s on ", stuck == hung ? "no progress" : "hang");
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for_each_engine_masked(engine, i915, hung, tmp)
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len += scnprintf(msg + len, sizeof(msg) - len,
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"%s, ", engine->name);
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msg[len-2] = '\0';
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return i915_handle_error(i915, hung, I915_ERROR_CAPTURE, "%s", msg);
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}
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/*
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* This is called when the chip hasn't reported back with completed
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* batchbuffers in a long time. We keep track per ring seqno progress and
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* if there are no progress, hangcheck score for that ring is increased.
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* Further, acthd is inspected to see if the ring is stuck. On stuck case
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* we kick the ring. If we see no progress on three subsequent calls
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* we assume chip is wedged and try to fix it by resetting the chip.
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*/
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static void i915_hangcheck_elapsed(struct work_struct *work)
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{
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struct drm_i915_private *dev_priv =
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container_of(work, typeof(*dev_priv),
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gpu_error.hangcheck_work.work);
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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unsigned int hung = 0, stuck = 0, wedged = 0;
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intel_wakeref_t wakeref;
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if (!i915_modparams.enable_hangcheck)
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return;
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if (!READ_ONCE(dev_priv->gt.awake))
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return;
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if (i915_terminally_wedged(dev_priv))
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return;
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wakeref = intel_runtime_pm_get_if_in_use(dev_priv);
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if (!wakeref)
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return;
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/* As enabling the GPU requires fairly extensive mmio access,
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* periodically arm the mmio checker to see if we are triggering
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* any invalid access.
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*/
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intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
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for_each_engine(engine, dev_priv, id) {
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struct hangcheck hc;
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intel_engine_signal_breadcrumbs(engine);
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hangcheck_load_sample(engine, &hc);
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hangcheck_accumulate_sample(engine, &hc);
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hangcheck_store_sample(engine, &hc);
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if (hc.stalled) {
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hung |= engine->mask;
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if (hc.action != ENGINE_DEAD)
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stuck |= engine->mask;
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}
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if (hc.wedged)
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wedged |= engine->mask;
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}
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if (GEM_SHOW_DEBUG() && (hung | stuck)) {
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struct drm_printer p = drm_debug_printer("hangcheck");
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for_each_engine(engine, dev_priv, id) {
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if (intel_engine_is_idle(engine))
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continue;
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intel_engine_dump(engine, &p, "%s\n", engine->name);
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}
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}
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if (wedged) {
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dev_err(dev_priv->drm.dev,
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"GPU recovery timed out,"
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" cancelling all in-flight rendering.\n");
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GEM_TRACE_DUMP();
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i915_gem_set_wedged(dev_priv);
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}
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if (hung)
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hangcheck_declare_hang(dev_priv, hung, stuck);
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intel_runtime_pm_put(dev_priv, wakeref);
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/* Reset timer in case GPU hangs without another request being added */
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i915_queue_hangcheck(dev_priv);
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}
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void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
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{
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memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
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engine->hangcheck.action_timestamp = jiffies;
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}
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void intel_hangcheck_init(struct drm_i915_private *i915)
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{
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INIT_DELAYED_WORK(&i915->gpu_error.hangcheck_work,
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i915_hangcheck_elapsed);
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}
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#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
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#include "selftest_hangcheck.c"
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#endif
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