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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1334 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.113240726@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
611 lines
14 KiB
C
611 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* SN Platform GRU Driver
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*
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* FILE OPERATIONS & DRIVER INITIALIZATION
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*
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* This file supports the user system call for file open, close, mmap, etc.
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* This also incudes the driver initialization code.
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*
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* Copyright (c) 2008-2014 Silicon Graphics, Inc. All Rights Reserved.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/device.h>
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#include <linux/miscdevice.h>
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#include <linux/interrupt.h>
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#include <linux/proc_fs.h>
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#include <linux/uaccess.h>
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#ifdef CONFIG_X86_64
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#include <asm/uv/uv_irq.h>
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#endif
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#include <asm/uv/uv.h>
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#include "gru.h"
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#include "grulib.h"
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#include "grutables.h"
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#include <asm/uv/uv_hub.h>
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#include <asm/uv/uv_mmrs.h>
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struct gru_blade_state *gru_base[GRU_MAX_BLADES] __read_mostly;
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unsigned long gru_start_paddr __read_mostly;
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void *gru_start_vaddr __read_mostly;
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unsigned long gru_end_paddr __read_mostly;
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unsigned int gru_max_gids __read_mostly;
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struct gru_stats_s gru_stats;
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/* Guaranteed user available resources on each node */
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static int max_user_cbrs, max_user_dsr_bytes;
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static struct miscdevice gru_miscdev;
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static int gru_supported(void)
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{
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return is_uv_system() &&
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(uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE);
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}
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/*
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* gru_vma_close
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*
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* Called when unmapping a device mapping. Frees all gru resources
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* and tables belonging to the vma.
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*/
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static void gru_vma_close(struct vm_area_struct *vma)
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{
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struct gru_vma_data *vdata;
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struct gru_thread_state *gts;
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struct list_head *entry, *next;
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if (!vma->vm_private_data)
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return;
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vdata = vma->vm_private_data;
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vma->vm_private_data = NULL;
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gru_dbg(grudev, "vma %p, file %p, vdata %p\n", vma, vma->vm_file,
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vdata);
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list_for_each_safe(entry, next, &vdata->vd_head) {
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gts =
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list_entry(entry, struct gru_thread_state, ts_next);
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list_del(>s->ts_next);
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mutex_lock(>s->ts_ctxlock);
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if (gts->ts_gru)
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gru_unload_context(gts, 0);
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mutex_unlock(>s->ts_ctxlock);
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gts_drop(gts);
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}
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kfree(vdata);
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STAT(vdata_free);
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}
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/*
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* gru_file_mmap
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*
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* Called when mmapping the device. Initializes the vma with a fault handler
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* and private data structure necessary to allocate, track, and free the
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* underlying pages.
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*/
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static int gru_file_mmap(struct file *file, struct vm_area_struct *vma)
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{
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if ((vma->vm_flags & (VM_SHARED | VM_WRITE)) != (VM_SHARED | VM_WRITE))
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return -EPERM;
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if (vma->vm_start & (GRU_GSEG_PAGESIZE - 1) ||
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vma->vm_end & (GRU_GSEG_PAGESIZE - 1))
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return -EINVAL;
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vma->vm_flags |= VM_IO | VM_PFNMAP | VM_LOCKED |
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VM_DONTCOPY | VM_DONTEXPAND | VM_DONTDUMP;
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vma->vm_page_prot = PAGE_SHARED;
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vma->vm_ops = &gru_vm_ops;
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vma->vm_private_data = gru_alloc_vma_data(vma, 0);
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if (!vma->vm_private_data)
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return -ENOMEM;
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gru_dbg(grudev, "file %p, vaddr 0x%lx, vma %p, vdata %p\n",
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file, vma->vm_start, vma, vma->vm_private_data);
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return 0;
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}
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/*
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* Create a new GRU context
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*/
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static int gru_create_new_context(unsigned long arg)
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{
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struct gru_create_context_req req;
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struct vm_area_struct *vma;
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struct gru_vma_data *vdata;
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int ret = -EINVAL;
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if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
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return -EFAULT;
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if (req.data_segment_bytes > max_user_dsr_bytes)
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return -EINVAL;
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if (req.control_blocks > max_user_cbrs || !req.maximum_thread_count)
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return -EINVAL;
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if (!(req.options & GRU_OPT_MISS_MASK))
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req.options |= GRU_OPT_MISS_FMM_INTR;
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down_write(¤t->mm->mmap_sem);
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vma = gru_find_vma(req.gseg);
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if (vma) {
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vdata = vma->vm_private_data;
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vdata->vd_user_options = req.options;
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vdata->vd_dsr_au_count =
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GRU_DS_BYTES_TO_AU(req.data_segment_bytes);
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vdata->vd_cbr_au_count = GRU_CB_COUNT_TO_AU(req.control_blocks);
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vdata->vd_tlb_preload_count = req.tlb_preload_count;
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ret = 0;
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}
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up_write(¤t->mm->mmap_sem);
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return ret;
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}
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/*
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* Get GRU configuration info (temp - for emulator testing)
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*/
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static long gru_get_config_info(unsigned long arg)
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{
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struct gru_config_info info;
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int nodesperblade;
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if (num_online_nodes() > 1 &&
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(uv_node_to_blade_id(1) == uv_node_to_blade_id(0)))
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nodesperblade = 2;
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else
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nodesperblade = 1;
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memset(&info, 0, sizeof(info));
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info.cpus = num_online_cpus();
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info.nodes = num_online_nodes();
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info.blades = info.nodes / nodesperblade;
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info.chiplets = GRU_CHIPLETS_PER_BLADE * info.blades;
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if (copy_to_user((void __user *)arg, &info, sizeof(info)))
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return -EFAULT;
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return 0;
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}
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/*
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* gru_file_unlocked_ioctl
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*
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* Called to update file attributes via IOCTL calls.
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*/
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static long gru_file_unlocked_ioctl(struct file *file, unsigned int req,
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unsigned long arg)
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{
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int err = -EBADRQC;
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gru_dbg(grudev, "file %p, req 0x%x, 0x%lx\n", file, req, arg);
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switch (req) {
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case GRU_CREATE_CONTEXT:
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err = gru_create_new_context(arg);
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break;
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case GRU_SET_CONTEXT_OPTION:
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err = gru_set_context_option(arg);
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break;
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case GRU_USER_GET_EXCEPTION_DETAIL:
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err = gru_get_exception_detail(arg);
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break;
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case GRU_USER_UNLOAD_CONTEXT:
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err = gru_user_unload_context(arg);
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break;
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case GRU_USER_FLUSH_TLB:
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err = gru_user_flush_tlb(arg);
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break;
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case GRU_USER_CALL_OS:
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err = gru_handle_user_call_os(arg);
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break;
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case GRU_GET_GSEG_STATISTICS:
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err = gru_get_gseg_statistics(arg);
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break;
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case GRU_KTEST:
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err = gru_ktest(arg);
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break;
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case GRU_GET_CONFIG_INFO:
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err = gru_get_config_info(arg);
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break;
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case GRU_DUMP_CHIPLET_STATE:
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err = gru_dump_chiplet_request(arg);
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break;
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}
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return err;
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}
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/*
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* Called at init time to build tables for all GRUs that are present in the
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* system.
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*/
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static void gru_init_chiplet(struct gru_state *gru, unsigned long paddr,
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void *vaddr, int blade_id, int chiplet_id)
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{
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spin_lock_init(&gru->gs_lock);
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spin_lock_init(&gru->gs_asid_lock);
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gru->gs_gru_base_paddr = paddr;
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gru->gs_gru_base_vaddr = vaddr;
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gru->gs_gid = blade_id * GRU_CHIPLETS_PER_BLADE + chiplet_id;
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gru->gs_blade = gru_base[blade_id];
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gru->gs_blade_id = blade_id;
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gru->gs_chiplet_id = chiplet_id;
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gru->gs_cbr_map = (GRU_CBR_AU == 64) ? ~0 : (1UL << GRU_CBR_AU) - 1;
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gru->gs_dsr_map = (1UL << GRU_DSR_AU) - 1;
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gru->gs_asid_limit = MAX_ASID;
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gru_tgh_flush_init(gru);
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if (gru->gs_gid >= gru_max_gids)
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gru_max_gids = gru->gs_gid + 1;
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gru_dbg(grudev, "bid %d, gid %d, vaddr %p (0x%lx)\n",
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blade_id, gru->gs_gid, gru->gs_gru_base_vaddr,
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gru->gs_gru_base_paddr);
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}
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static int gru_init_tables(unsigned long gru_base_paddr, void *gru_base_vaddr)
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{
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int pnode, nid, bid, chip;
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int cbrs, dsrbytes, n;
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int order = get_order(sizeof(struct gru_blade_state));
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struct page *page;
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struct gru_state *gru;
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unsigned long paddr;
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void *vaddr;
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max_user_cbrs = GRU_NUM_CB;
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max_user_dsr_bytes = GRU_NUM_DSR_BYTES;
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for_each_possible_blade(bid) {
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pnode = uv_blade_to_pnode(bid);
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nid = uv_blade_to_memory_nid(bid);/* -1 if no memory on blade */
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page = alloc_pages_node(nid, GFP_KERNEL, order);
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if (!page)
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goto fail;
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gru_base[bid] = page_address(page);
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memset(gru_base[bid], 0, sizeof(struct gru_blade_state));
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gru_base[bid]->bs_lru_gru = &gru_base[bid]->bs_grus[0];
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spin_lock_init(&gru_base[bid]->bs_lock);
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init_rwsem(&gru_base[bid]->bs_kgts_sema);
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dsrbytes = 0;
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cbrs = 0;
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for (gru = gru_base[bid]->bs_grus, chip = 0;
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chip < GRU_CHIPLETS_PER_BLADE;
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chip++, gru++) {
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paddr = gru_chiplet_paddr(gru_base_paddr, pnode, chip);
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vaddr = gru_chiplet_vaddr(gru_base_vaddr, pnode, chip);
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gru_init_chiplet(gru, paddr, vaddr, bid, chip);
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n = hweight64(gru->gs_cbr_map) * GRU_CBR_AU_SIZE;
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cbrs = max(cbrs, n);
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n = hweight64(gru->gs_dsr_map) * GRU_DSR_AU_BYTES;
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dsrbytes = max(dsrbytes, n);
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}
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max_user_cbrs = min(max_user_cbrs, cbrs);
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max_user_dsr_bytes = min(max_user_dsr_bytes, dsrbytes);
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}
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return 0;
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fail:
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for (bid--; bid >= 0; bid--)
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free_pages((unsigned long)gru_base[bid], order);
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return -ENOMEM;
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}
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static void gru_free_tables(void)
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{
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int bid;
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int order = get_order(sizeof(struct gru_state) *
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GRU_CHIPLETS_PER_BLADE);
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for (bid = 0; bid < GRU_MAX_BLADES; bid++)
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free_pages((unsigned long)gru_base[bid], order);
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}
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static unsigned long gru_chiplet_cpu_to_mmr(int chiplet, int cpu, int *corep)
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{
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unsigned long mmr = 0;
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int core;
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/*
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* We target the cores of a blade and not the hyperthreads themselves.
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* There is a max of 8 cores per socket and 2 sockets per blade,
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* making for a max total of 16 cores (i.e., 16 CPUs without
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* hyperthreading and 32 CPUs with hyperthreading).
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*/
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core = uv_cpu_core_number(cpu) + UV_MAX_INT_CORES * uv_cpu_socket_number(cpu);
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if (core >= GRU_NUM_TFM || uv_cpu_ht_number(cpu))
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return 0;
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if (chiplet == 0) {
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mmr = UVH_GR0_TLB_INT0_CONFIG +
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core * (UVH_GR0_TLB_INT1_CONFIG - UVH_GR0_TLB_INT0_CONFIG);
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} else if (chiplet == 1) {
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mmr = UVH_GR1_TLB_INT0_CONFIG +
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core * (UVH_GR1_TLB_INT1_CONFIG - UVH_GR1_TLB_INT0_CONFIG);
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} else {
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BUG();
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}
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*corep = core;
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return mmr;
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}
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#ifdef CONFIG_IA64
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static int gru_irq_count[GRU_CHIPLETS_PER_BLADE];
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static void gru_noop(struct irq_data *d)
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{
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}
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static struct irq_chip gru_chip[GRU_CHIPLETS_PER_BLADE] = {
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[0 ... GRU_CHIPLETS_PER_BLADE - 1] {
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.irq_mask = gru_noop,
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.irq_unmask = gru_noop,
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.irq_ack = gru_noop
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}
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};
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static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
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irq_handler_t irq_handler, int cpu, int blade)
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{
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unsigned long mmr;
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int irq = IRQ_GRU + chiplet;
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int ret, core;
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mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
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if (mmr == 0)
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return 0;
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if (gru_irq_count[chiplet] == 0) {
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gru_chip[chiplet].name = irq_name;
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ret = irq_set_chip(irq, &gru_chip[chiplet]);
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if (ret) {
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printk(KERN_ERR "%s: set_irq_chip failed, errno=%d\n",
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GRU_DRIVER_ID_STR, -ret);
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return ret;
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}
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ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
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if (ret) {
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printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
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GRU_DRIVER_ID_STR, -ret);
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return ret;
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}
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}
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gru_irq_count[chiplet]++;
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return 0;
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}
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static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
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{
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unsigned long mmr;
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int core, irq = IRQ_GRU + chiplet;
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if (gru_irq_count[chiplet] == 0)
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return;
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mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
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if (mmr == 0)
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return;
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if (--gru_irq_count[chiplet] == 0)
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free_irq(irq, NULL);
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}
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#elif defined CONFIG_X86_64
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static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
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irq_handler_t irq_handler, int cpu, int blade)
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{
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unsigned long mmr;
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int irq, core;
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int ret;
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mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
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if (mmr == 0)
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return 0;
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irq = uv_setup_irq(irq_name, cpu, blade, mmr, UV_AFFINITY_CPU);
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if (irq < 0) {
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printk(KERN_ERR "%s: uv_setup_irq failed, errno=%d\n",
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GRU_DRIVER_ID_STR, -irq);
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return irq;
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}
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ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
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if (ret) {
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uv_teardown_irq(irq);
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printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
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GRU_DRIVER_ID_STR, -ret);
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return ret;
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}
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gru_base[blade]->bs_grus[chiplet].gs_irq[core] = irq;
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return 0;
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}
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static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
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{
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int irq, core;
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unsigned long mmr;
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mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
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if (mmr) {
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irq = gru_base[blade]->bs_grus[chiplet].gs_irq[core];
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if (irq) {
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free_irq(irq, NULL);
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uv_teardown_irq(irq);
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}
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}
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}
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#endif
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static void gru_teardown_tlb_irqs(void)
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{
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int blade;
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int cpu;
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for_each_online_cpu(cpu) {
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blade = uv_cpu_to_blade_id(cpu);
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gru_chiplet_teardown_tlb_irq(0, cpu, blade);
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gru_chiplet_teardown_tlb_irq(1, cpu, blade);
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}
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for_each_possible_blade(blade) {
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|
if (uv_blade_nr_possible_cpus(blade))
|
|
continue;
|
|
gru_chiplet_teardown_tlb_irq(0, 0, blade);
|
|
gru_chiplet_teardown_tlb_irq(1, 0, blade);
|
|
}
|
|
}
|
|
|
|
static int gru_setup_tlb_irqs(void)
|
|
{
|
|
int blade;
|
|
int cpu;
|
|
int ret;
|
|
|
|
for_each_online_cpu(cpu) {
|
|
blade = uv_cpu_to_blade_id(cpu);
|
|
ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru0_intr, cpu, blade);
|
|
if (ret != 0)
|
|
goto exit1;
|
|
|
|
ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru1_intr, cpu, blade);
|
|
if (ret != 0)
|
|
goto exit1;
|
|
}
|
|
for_each_possible_blade(blade) {
|
|
if (uv_blade_nr_possible_cpus(blade))
|
|
continue;
|
|
ret = gru_chiplet_setup_tlb_irq(0, "GRU0_TLB", gru_intr_mblade, 0, blade);
|
|
if (ret != 0)
|
|
goto exit1;
|
|
|
|
ret = gru_chiplet_setup_tlb_irq(1, "GRU1_TLB", gru_intr_mblade, 0, blade);
|
|
if (ret != 0)
|
|
goto exit1;
|
|
}
|
|
|
|
return 0;
|
|
|
|
exit1:
|
|
gru_teardown_tlb_irqs();
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* gru_init
|
|
*
|
|
* Called at boot or module load time to initialize the GRUs.
|
|
*/
|
|
static int __init gru_init(void)
|
|
{
|
|
int ret;
|
|
|
|
if (!gru_supported())
|
|
return 0;
|
|
|
|
#if defined CONFIG_IA64
|
|
gru_start_paddr = 0xd000000000UL; /* ZZZZZZZZZZZZZZZZZZZ fixme */
|
|
#else
|
|
gru_start_paddr = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR) &
|
|
0x7fffffffffffUL;
|
|
#endif
|
|
gru_start_vaddr = __va(gru_start_paddr);
|
|
gru_end_paddr = gru_start_paddr + GRU_MAX_BLADES * GRU_SIZE;
|
|
printk(KERN_INFO "GRU space: 0x%lx - 0x%lx\n",
|
|
gru_start_paddr, gru_end_paddr);
|
|
ret = misc_register(&gru_miscdev);
|
|
if (ret) {
|
|
printk(KERN_ERR "%s: misc_register failed\n",
|
|
GRU_DRIVER_ID_STR);
|
|
goto exit0;
|
|
}
|
|
|
|
ret = gru_proc_init();
|
|
if (ret) {
|
|
printk(KERN_ERR "%s: proc init failed\n", GRU_DRIVER_ID_STR);
|
|
goto exit1;
|
|
}
|
|
|
|
ret = gru_init_tables(gru_start_paddr, gru_start_vaddr);
|
|
if (ret) {
|
|
printk(KERN_ERR "%s: init tables failed\n", GRU_DRIVER_ID_STR);
|
|
goto exit2;
|
|
}
|
|
|
|
ret = gru_setup_tlb_irqs();
|
|
if (ret != 0)
|
|
goto exit3;
|
|
|
|
gru_kservices_init();
|
|
|
|
printk(KERN_INFO "%s: v%s\n", GRU_DRIVER_ID_STR,
|
|
GRU_DRIVER_VERSION_STR);
|
|
return 0;
|
|
|
|
exit3:
|
|
gru_free_tables();
|
|
exit2:
|
|
gru_proc_exit();
|
|
exit1:
|
|
misc_deregister(&gru_miscdev);
|
|
exit0:
|
|
return ret;
|
|
|
|
}
|
|
|
|
static void __exit gru_exit(void)
|
|
{
|
|
if (!gru_supported())
|
|
return;
|
|
|
|
gru_teardown_tlb_irqs();
|
|
gru_kservices_exit();
|
|
gru_free_tables();
|
|
misc_deregister(&gru_miscdev);
|
|
gru_proc_exit();
|
|
}
|
|
|
|
static const struct file_operations gru_fops = {
|
|
.owner = THIS_MODULE,
|
|
.unlocked_ioctl = gru_file_unlocked_ioctl,
|
|
.mmap = gru_file_mmap,
|
|
.llseek = noop_llseek,
|
|
};
|
|
|
|
static struct miscdevice gru_miscdev = {
|
|
.minor = MISC_DYNAMIC_MINOR,
|
|
.name = "gru",
|
|
.fops = &gru_fops,
|
|
};
|
|
|
|
const struct vm_operations_struct gru_vm_ops = {
|
|
.close = gru_vma_close,
|
|
.fault = gru_fault,
|
|
};
|
|
|
|
#ifndef MODULE
|
|
fs_initcall(gru_init);
|
|
#else
|
|
module_init(gru_init);
|
|
#endif
|
|
module_exit(gru_exit);
|
|
|
|
module_param(gru_options, ulong, 0644);
|
|
MODULE_PARM_DESC(gru_options, "Various debug options");
|
|
|
|
MODULE_AUTHOR("Silicon Graphics, Inc.");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION(GRU_DRIVER_ID_STR GRU_DRIVER_VERSION_STR);
|
|
MODULE_VERSION(GRU_DRIVER_VERSION_STR);
|
|
|