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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1085fdc68c
Introduce a new KVM device that represents an ARM Interrupt Translation Service (ITS) controller. Since there can be multiple of this per guest, we can't piggy back on the existing GICv3 distributor device, but create a new type of KVM device. On the KVM_CREATE_DEVICE ioctl we allocate and initialize the ITS data structure and store the pointer in the kvm_device data. Upon an explicit init ioctl from userland (after having setup the MMIO address) we register the handlers with the kvm_io_bus framework. Any reference to an ITS thus has to go via this interface. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
239 lines
5.5 KiB
C
239 lines
5.5 KiB
C
/*
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* GICv3 ITS emulation
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*
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* Copyright (C) 2015,2016 ARM Ltd.
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* Author: Andre Przywara <andre.przywara@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/cpu.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/interrupt.h>
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#include <linux/uaccess.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_mmu.h>
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#include "vgic.h"
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#include "vgic-mmio.h"
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#define REGISTER_ITS_DESC(off, rd, wr, length, acc) \
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{ \
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.reg_offset = off, \
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.len = length, \
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.access_flags = acc, \
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.its_read = rd, \
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.its_write = wr, \
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}
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static unsigned long its_mmio_read_raz(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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return 0;
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}
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static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len, unsigned long val)
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{
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/* Ignore */
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}
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static struct vgic_register_region its_registers[] = {
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REGISTER_ITS_DESC(GITS_CTLR,
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its_mmio_read_raz, its_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_IIDR,
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its_mmio_read_raz, its_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_TYPER,
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its_mmio_read_raz, its_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_CBASER,
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its_mmio_read_raz, its_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_CWRITER,
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its_mmio_read_raz, its_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_CREADR,
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its_mmio_read_raz, its_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_BASER,
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its_mmio_read_raz, its_mmio_write_wi, 0x40,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_IDREGS_BASE,
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its_mmio_read_raz, its_mmio_write_wi, 0x30,
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VGIC_ACCESS_32bit),
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};
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static int vgic_its_init_its(struct kvm *kvm, struct vgic_its *its)
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{
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struct vgic_io_device *iodev = &its->iodev;
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int ret;
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if (its->initialized)
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return 0;
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if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base))
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return -ENXIO;
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iodev->regions = its_registers;
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iodev->nr_regions = ARRAY_SIZE(its_registers);
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kvm_iodevice_init(&iodev->dev, &kvm_io_gic_ops);
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iodev->base_addr = its->vgic_its_base;
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iodev->iodev_type = IODEV_ITS;
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iodev->its = its;
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mutex_lock(&kvm->slots_lock);
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ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, iodev->base_addr,
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KVM_VGIC_V3_ITS_SIZE, &iodev->dev);
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mutex_unlock(&kvm->slots_lock);
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if (!ret)
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its->initialized = true;
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return ret;
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}
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static int vgic_its_create(struct kvm_device *dev, u32 type)
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{
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struct vgic_its *its;
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if (type != KVM_DEV_TYPE_ARM_VGIC_ITS)
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return -ENODEV;
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its = kzalloc(sizeof(struct vgic_its), GFP_KERNEL);
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if (!its)
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return -ENOMEM;
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its->vgic_its_base = VGIC_ADDR_UNDEF;
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dev->kvm->arch.vgic.has_its = true;
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its->initialized = false;
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its->enabled = false;
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dev->private = its;
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return 0;
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}
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static void vgic_its_destroy(struct kvm_device *kvm_dev)
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{
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struct vgic_its *its = kvm_dev->private;
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kfree(its);
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}
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static int vgic_its_has_attr(struct kvm_device *dev,
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struct kvm_device_attr *attr)
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{
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switch (attr->group) {
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case KVM_DEV_ARM_VGIC_GRP_ADDR:
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switch (attr->attr) {
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case KVM_VGIC_ITS_ADDR_TYPE:
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return 0;
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}
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break;
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case KVM_DEV_ARM_VGIC_GRP_CTRL:
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switch (attr->attr) {
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case KVM_DEV_ARM_VGIC_CTRL_INIT:
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return 0;
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}
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break;
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}
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return -ENXIO;
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}
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static int vgic_its_set_attr(struct kvm_device *dev,
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struct kvm_device_attr *attr)
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{
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struct vgic_its *its = dev->private;
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int ret;
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switch (attr->group) {
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case KVM_DEV_ARM_VGIC_GRP_ADDR: {
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u64 __user *uaddr = (u64 __user *)(long)attr->addr;
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unsigned long type = (unsigned long)attr->attr;
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u64 addr;
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if (type != KVM_VGIC_ITS_ADDR_TYPE)
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return -ENODEV;
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if (its->initialized)
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return -EBUSY;
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if (copy_from_user(&addr, uaddr, sizeof(addr)))
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return -EFAULT;
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ret = vgic_check_ioaddr(dev->kvm, &its->vgic_its_base,
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addr, SZ_64K);
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if (ret)
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return ret;
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its->vgic_its_base = addr;
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return 0;
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}
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case KVM_DEV_ARM_VGIC_GRP_CTRL:
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switch (attr->attr) {
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case KVM_DEV_ARM_VGIC_CTRL_INIT:
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return vgic_its_init_its(dev->kvm, its);
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}
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break;
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}
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return -ENXIO;
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}
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static int vgic_its_get_attr(struct kvm_device *dev,
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struct kvm_device_attr *attr)
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{
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switch (attr->group) {
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case KVM_DEV_ARM_VGIC_GRP_ADDR: {
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struct vgic_its *its = dev->private;
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u64 addr = its->vgic_its_base;
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u64 __user *uaddr = (u64 __user *)(long)attr->addr;
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unsigned long type = (unsigned long)attr->attr;
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if (type != KVM_VGIC_ITS_ADDR_TYPE)
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return -ENODEV;
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if (copy_to_user(uaddr, &addr, sizeof(addr)))
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return -EFAULT;
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break;
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default:
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return -ENXIO;
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}
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}
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return 0;
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}
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static struct kvm_device_ops kvm_arm_vgic_its_ops = {
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.name = "kvm-arm-vgic-its",
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.create = vgic_its_create,
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.destroy = vgic_its_destroy,
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.set_attr = vgic_its_set_attr,
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.get_attr = vgic_its_get_attr,
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.has_attr = vgic_its_has_attr,
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};
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int kvm_vgic_register_its_device(void)
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{
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return kvm_register_device_ops(&kvm_arm_vgic_its_ops,
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KVM_DEV_TYPE_ARM_VGIC_ITS);
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}
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