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The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort Subsystem. It includes a buffer manager, a video pipeline renderer (blender), an audio mixer and a DisplayPort source controller (transmitter). The DMA engine the provide data to the buffer manager, as well as the DisplayPort PHYs that drive the lanes, are external to the subsystem and interfaced using the DMA engine and PHY APIs respectively. This driver supports the DisplayPort Subsystem and implements - Two planes, for graphics and video - One CRTC that supports alpha blending - One encoder for the DisplayPort transmitter - One connector for an external monitor It currently doesn't support - Color keying - Test pattern generation - Audio - Live input from the Programmable Logic (FPGA) - Output to the Programmable Logic (FPGA) Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
202 lines
9.5 KiB
C
202 lines
9.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ZynqMP Display Controller Driver - Register Definitions
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*
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* Copyright (C) 2017 - 2020 Xilinx, Inc.
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*
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* Authors:
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* - Hyun Woo Kwon <hyun.kwon@xilinx.com>
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* - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#ifndef _ZYNQMP_DISP_REGS_H_
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#define _ZYNQMP_DISP_REGS_H_
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#include <linux/bits.h>
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/* Blender registers */
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#define ZYNQMP_DISP_V_BLEND_BG_CLR_0 0x0
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#define ZYNQMP_DISP_V_BLEND_BG_CLR_1 0x4
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#define ZYNQMP_DISP_V_BLEND_BG_CLR_2 0x8
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#define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff
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#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA 0xc
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#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(n) ((n) << 1)
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#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN BIT(0)
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#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x14
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#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB 0x0
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#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444 0x1
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#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422 0x2
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#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY 0x3
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#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC 0x4
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#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE BIT(4)
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#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(n) (0x18 + ((n) * 4))
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#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US BIT(0)
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#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB BIT(1)
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#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS BIT(8)
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#define ZYNQMP_DISP_V_BLEND_NUM_COEFF 9
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#define ZYNQMP_DISP_V_BLEND_NUM_OFFSET 3
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#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(n) (0x20 + ((n) * 4))
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#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(n) (0x44 + ((n) * 4))
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#define ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(n) (0x68 + ((n) * 4))
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#define ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(n) (0x74 + ((n) * 4))
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#define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(n) (0x80 + ((n) * 4))
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#define ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(n) (0xa4 + ((n) * 4))
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#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_ENABLE 0x1d0
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#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP1 0x1d4
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#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP2 0x1d8
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#define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP3 0x1dc
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/* AV buffer manager registers */
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#define ZYNQMP_DISP_AV_BUF_FMT 0x0
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_SHIFT 0
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK (0x1f << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_UYVY (0 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY (1 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YVYU (2 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV (3 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16 (4 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24 (5 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI (6 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MONO (7 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2 (8 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444 (9 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888 (10 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880 (11 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10 (12 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444_10 (13 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_10 (14 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10 (15 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_10 (16 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24_10 (17 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YONLY_10 (18 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420 (19 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420 (20 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420 (21 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420_10 (22 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420_10 (23 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420_10 (24 << 0)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_SHIFT 8
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK (0xf << 8)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888 (0 << 8)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888 (1 << 8)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888 (2 << 8)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888 (3 << 8)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551 (4 << 8)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444 (5 << 8)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565 (6 << 8)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_8BPP (7 << 8)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_4BPP (8 << 8)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_2BPP (9 << 8)
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#define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_1BPP (10 << 8)
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#define ZYNQMP_DISP_AV_BUF_NON_LIVE_LATENCY 0x8
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#define ZYNQMP_DISP_AV_BUF_CHBUF(n) (0x10 + ((n) * 4))
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#define ZYNQMP_DISP_AV_BUF_CHBUF_EN BIT(0)
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#define ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH BIT(1)
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#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT 2
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#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MASK (0xf << 2)
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#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX 0xf
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#define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX 0x3
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#define ZYNQMP_DISP_AV_BUF_STATUS 0x28
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#define ZYNQMP_DISP_AV_BUF_STC_CTRL 0x2c
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#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EN BIT(0)
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#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_SHIFT 1
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#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_VSYNC 0
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#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_VID 1
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#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_AUD 2
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#define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_INT_VSYNC 3
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#define ZYNQMP_DISP_AV_BUF_STC_INIT_VALUE0 0x30
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#define ZYNQMP_DISP_AV_BUF_STC_INIT_VALUE1 0x34
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#define ZYNQMP_DISP_AV_BUF_STC_ADJ 0x38
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#define ZYNQMP_DISP_AV_BUF_STC_VID_VSYNC_TS0 0x3c
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#define ZYNQMP_DISP_AV_BUF_STC_VID_VSYNC_TS1 0x40
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#define ZYNQMP_DISP_AV_BUF_STC_EXT_VSYNC_TS0 0x44
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#define ZYNQMP_DISP_AV_BUF_STC_EXT_VSYNC_TS1 0x48
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#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT_TS0 0x4c
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#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT_TS1 0x50
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#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT2_TS0 0x54
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#define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT2_TS1 0x58
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#define ZYNQMP_DISP_AV_BUF_STC_SNAPSHOT0 0x60
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#define ZYNQMP_DISP_AV_BUF_STC_SNAPSHOT1 0x64
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#define ZYNQMP_DISP_AV_BUF_OUTPUT 0x70
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_SHIFT 0
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK (0x3 << 0)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE (0 << 0)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM (1 << 0)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_PATTERN (2 << 0)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE (3 << 0)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_SHIFT 2
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK (0x3 << 2)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE (0 << 2)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM (1 << 2)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE (2 << 2)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_NONE (3 << 2)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_SHIFT 4
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK (0x3 << 4)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PL (0 << 4)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM (1 << 4)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PATTERN (2 << 4)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE (3 << 4)
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#define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN BIT(6)
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#define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT0 0x74
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#define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT1 0x78
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#define ZYNQMP_DISP_AV_BUF_PATTERN_GEN_SELECT 0x100
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#define ZYNQMP_DISP_AV_BUF_CLK_SRC 0x120
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#define ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS BIT(0)
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#define ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS BIT(1)
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#define ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING BIT(2)
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#define ZYNQMP_DISP_AV_BUF_SRST_REG 0x124
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#define ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST BIT(1)
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#define ZYNQMP_DISP_AV_BUF_AUDIO_CH_CONFIG 0x12c
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#define ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(n) (0x200 + ((n) * 4))
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#define ZYNQMP_DISP_AV_BUF_VID_COMP_SF(n) (0x20c + ((n) * 4))
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#define ZYNQMP_DISP_AV_BUF_LIVD_VID_COMP_SF(n) (0x218 + ((n) * 4))
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#define ZYNQMP_DISP_AV_BUF_LIVE_VID_CONFIG 0x224
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#define ZYNQMP_DISP_AV_BUF_LIVD_GFX_COMP_SF(n) (0x228 + ((n) * 4))
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#define ZYNQMP_DISP_AV_BUF_LIVE_GFX_CONFIG 0x234
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#define ZYNQMP_DISP_AV_BUF_4BIT_SF 0x11111
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#define ZYNQMP_DISP_AV_BUF_5BIT_SF 0x10842
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#define ZYNQMP_DISP_AV_BUF_6BIT_SF 0x10410
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#define ZYNQMP_DISP_AV_BUF_8BIT_SF 0x10101
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#define ZYNQMP_DISP_AV_BUF_10BIT_SF 0x10040
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#define ZYNQMP_DISP_AV_BUF_NULL_SF 0
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#define ZYNQMP_DISP_AV_BUF_NUM_SF 3
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#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_6 0x0
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#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 0x1
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#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_10 0x2
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#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_12 0x3
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#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_MASK GENMASK(2, 0)
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#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB 0x0
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#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444 0x1
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#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422 0x2
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#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YONLY 0x3
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#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_MASK GENMASK(5, 4)
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#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_CB_FIRST BIT(8)
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#define ZYNQMP_DISP_AV_BUF_PALETTE_MEMORY 0x400
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/* Audio registers */
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#define ZYNQMP_DISP_AUD_MIXER_VOLUME 0x0
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#define ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE 0x20002000
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#define ZYNQMP_DISP_AUD_MIXER_META_DATA 0x4
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#define ZYNQMP_DISP_AUD_CH_STATUS0 0x8
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#define ZYNQMP_DISP_AUD_CH_STATUS1 0xc
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#define ZYNQMP_DISP_AUD_CH_STATUS2 0x10
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#define ZYNQMP_DISP_AUD_CH_STATUS3 0x14
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#define ZYNQMP_DISP_AUD_CH_STATUS4 0x18
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#define ZYNQMP_DISP_AUD_CH_STATUS5 0x1c
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#define ZYNQMP_DISP_AUD_CH_A_DATA0 0x20
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#define ZYNQMP_DISP_AUD_CH_A_DATA1 0x24
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#define ZYNQMP_DISP_AUD_CH_A_DATA2 0x28
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#define ZYNQMP_DISP_AUD_CH_A_DATA3 0x2c
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#define ZYNQMP_DISP_AUD_CH_A_DATA4 0x30
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#define ZYNQMP_DISP_AUD_CH_A_DATA5 0x34
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#define ZYNQMP_DISP_AUD_CH_B_DATA0 0x38
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#define ZYNQMP_DISP_AUD_CH_B_DATA1 0x3c
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#define ZYNQMP_DISP_AUD_CH_B_DATA2 0x40
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#define ZYNQMP_DISP_AUD_CH_B_DATA3 0x44
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#define ZYNQMP_DISP_AUD_CH_B_DATA4 0x48
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#define ZYNQMP_DISP_AUD_CH_B_DATA5 0x4c
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#define ZYNQMP_DISP_AUD_SOFT_RESET 0xc00
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#define ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST BIT(0)
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#endif /* _ZYNQMP_DISP_REGS_H_ */
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