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09dcd1958b
This new header file is for NPS400 SoC (part of ARC architecture). The header file includes macros for save/restore of HW scheduling. The control of HW scheduling is achieved by writing core registers. This code was moved from arc/plat-eznps so it can be used from drivers/clocksource/, available only for CONFIG_EZNPS_MTM_EXT. Signed-off-by: Noam Camus <noamca@mellanox.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
60 lines
2.0 KiB
C
60 lines
2.0 KiB
C
/*
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* Copyright (c) 2016, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef SOC_NPS_MTM_H
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#define SOC_NPS_MTM_H
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#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF
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#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3
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static inline void hw_schd_save(unsigned int *flags)
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{
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__asm__ __volatile__(
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" .word %1\n"
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" st r3,[%0]\n"
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:
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: "r"(flags), "i"(CTOP_INST_HWSCHD_OFF_R3)
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: "r3", "memory");
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}
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static inline void hw_schd_restore(unsigned int flags)
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{
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__asm__ __volatile__(
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" mov r3, %0\n"
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" .word %1\n"
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:
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: "r"(flags), "i"(CTOP_INST_HWSCHD_RESTORE_R3)
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: "r3");
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}
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#endif /* SOC_NPS_MTM_H */
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