mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 10:26:40 +07:00
3cf6a06799
The sp810 clk driver is calling the clk consumer APIs from clk_prepare ops to change the parent to a 1 MHz fixed rate clock for each of the clocks that the driver provides. Use assigned-clock-parents for this instead of doing it in the driver to avoid using the consumer API in provider code. This also allows us to remove the usage of clk provider APIs that take a struct clk as an argument from the sp810 driver. Cc: Pawel Moll <pawel.moll@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
442 lines
10 KiB
Plaintext
442 lines
10 KiB
Plaintext
/*
|
|
* ARM Ltd. Versatile Express
|
|
*
|
|
* Motherboard Express uATX
|
|
* V2M-P1
|
|
*
|
|
* HBI-0190D
|
|
*
|
|
* Original memory map ("Legacy memory map" in the board's
|
|
* Technical Reference Manual)
|
|
*
|
|
* WARNING! The hardware described in this file is independent from the
|
|
* RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
|
|
* correspondence between the two configurations.
|
|
*
|
|
* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
|
|
* CHANGES TO vexpress-v2m-rs1.dtsi!
|
|
*/
|
|
|
|
motherboard {
|
|
model = "V2M-P1";
|
|
arm,hbi = <0x190>;
|
|
arm,vexpress,site = <0>;
|
|
compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
|
#address-cells = <2>; /* SMB chipselect number and offset */
|
|
#size-cells = <1>;
|
|
#interrupt-cells = <1>;
|
|
ranges;
|
|
|
|
flash@0,00000000 {
|
|
compatible = "arm,vexpress-flash", "cfi-flash";
|
|
reg = <0 0x00000000 0x04000000>,
|
|
<1 0x00000000 0x04000000>;
|
|
bank-width = <4>;
|
|
};
|
|
|
|
psram@2,00000000 {
|
|
compatible = "arm,vexpress-psram", "mtd-ram";
|
|
reg = <2 0x00000000 0x02000000>;
|
|
bank-width = <4>;
|
|
};
|
|
|
|
v2m_video_ram: vram@3,00000000 {
|
|
compatible = "arm,vexpress-vram";
|
|
reg = <3 0x00000000 0x00800000>;
|
|
};
|
|
|
|
ethernet@3,02000000 {
|
|
compatible = "smsc,lan9118", "smsc,lan9115";
|
|
reg = <3 0x02000000 0x10000>;
|
|
interrupts = <15>;
|
|
phy-mode = "mii";
|
|
reg-io-width = <4>;
|
|
smsc,irq-active-high;
|
|
smsc,irq-push-pull;
|
|
vdd33a-supply = <&v2m_fixed_3v3>;
|
|
vddvario-supply = <&v2m_fixed_3v3>;
|
|
};
|
|
|
|
usb@3,03000000 {
|
|
compatible = "nxp,usb-isp1761";
|
|
reg = <3 0x03000000 0x20000>;
|
|
interrupts = <16>;
|
|
port1-otg;
|
|
};
|
|
|
|
iofpga@7,00000000 {
|
|
compatible = "arm,amba-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 7 0 0x20000>;
|
|
|
|
v2m_sysreg: sysreg@00000 {
|
|
compatible = "arm,vexpress-sysreg";
|
|
reg = <0x00000 0x1000>;
|
|
|
|
v2m_led_gpios: sys_led@08 {
|
|
compatible = "arm,vexpress-sysreg,sys_led";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
v2m_mmc_gpios: sys_mci@48 {
|
|
compatible = "arm,vexpress-sysreg,sys_mci";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
|
|
v2m_flash_gpios: sys_flash@4c {
|
|
compatible = "arm,vexpress-sysreg,sys_flash";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
};
|
|
|
|
v2m_sysctl: sysctl@01000 {
|
|
compatible = "arm,sp810", "arm,primecell";
|
|
reg = <0x01000 0x1000>;
|
|
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
|
|
clock-names = "refclk", "timclk", "apb_pclk";
|
|
#clock-cells = <1>;
|
|
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
|
|
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
|
|
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
|
|
};
|
|
|
|
/* PCI-E I2C bus */
|
|
v2m_i2c_pcie: i2c@02000 {
|
|
compatible = "arm,versatile-i2c";
|
|
reg = <0x02000 0x1000>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pcie-switch@60 {
|
|
compatible = "idt,89hpes32h8";
|
|
reg = <0x60>;
|
|
};
|
|
};
|
|
|
|
aaci@04000 {
|
|
compatible = "arm,pl041", "arm,primecell";
|
|
reg = <0x04000 0x1000>;
|
|
interrupts = <11>;
|
|
clocks = <&smbclk>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
mmci@05000 {
|
|
compatible = "arm,pl180", "arm,primecell";
|
|
reg = <0x05000 0x1000>;
|
|
interrupts = <9 10>;
|
|
cd-gpios = <&v2m_mmc_gpios 0 0>;
|
|
wp-gpios = <&v2m_mmc_gpios 1 0>;
|
|
max-frequency = <12000000>;
|
|
vmmc-supply = <&v2m_fixed_3v3>;
|
|
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
};
|
|
|
|
kmi@06000 {
|
|
compatible = "arm,pl050", "arm,primecell";
|
|
reg = <0x06000 0x1000>;
|
|
interrupts = <12>;
|
|
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
|
clock-names = "KMIREFCLK", "apb_pclk";
|
|
};
|
|
|
|
kmi@07000 {
|
|
compatible = "arm,pl050", "arm,primecell";
|
|
reg = <0x07000 0x1000>;
|
|
interrupts = <13>;
|
|
clocks = <&v2m_clk24mhz>, <&smbclk>;
|
|
clock-names = "KMIREFCLK", "apb_pclk";
|
|
};
|
|
|
|
v2m_serial0: uart@09000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x09000 0x1000>;
|
|
interrupts = <5>;
|
|
clocks = <&v2m_oscclk2>, <&smbclk>;
|
|
clock-names = "uartclk", "apb_pclk";
|
|
};
|
|
|
|
v2m_serial1: uart@0a000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x0a000 0x1000>;
|
|
interrupts = <6>;
|
|
clocks = <&v2m_oscclk2>, <&smbclk>;
|
|
clock-names = "uartclk", "apb_pclk";
|
|
};
|
|
|
|
v2m_serial2: uart@0b000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x0b000 0x1000>;
|
|
interrupts = <7>;
|
|
clocks = <&v2m_oscclk2>, <&smbclk>;
|
|
clock-names = "uartclk", "apb_pclk";
|
|
};
|
|
|
|
v2m_serial3: uart@0c000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x0c000 0x1000>;
|
|
interrupts = <8>;
|
|
clocks = <&v2m_oscclk2>, <&smbclk>;
|
|
clock-names = "uartclk", "apb_pclk";
|
|
};
|
|
|
|
wdt@0f000 {
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
reg = <0x0f000 0x1000>;
|
|
interrupts = <0>;
|
|
clocks = <&v2m_refclk32khz>, <&smbclk>;
|
|
clock-names = "wdogclk", "apb_pclk";
|
|
};
|
|
|
|
v2m_timer01: timer@11000 {
|
|
compatible = "arm,sp804", "arm,primecell";
|
|
reg = <0x11000 0x1000>;
|
|
interrupts = <2>;
|
|
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
|
|
clock-names = "timclken1", "timclken2", "apb_pclk";
|
|
};
|
|
|
|
v2m_timer23: timer@12000 {
|
|
compatible = "arm,sp804", "arm,primecell";
|
|
reg = <0x12000 0x1000>;
|
|
interrupts = <3>;
|
|
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
|
|
clock-names = "timclken1", "timclken2", "apb_pclk";
|
|
};
|
|
|
|
/* DVI I2C bus */
|
|
v2m_i2c_dvi: i2c@16000 {
|
|
compatible = "arm,versatile-i2c";
|
|
reg = <0x16000 0x1000>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
dvi-transmitter@39 {
|
|
compatible = "sil,sii9022-tpi", "sil,sii9022";
|
|
reg = <0x39>;
|
|
};
|
|
|
|
dvi-transmitter@60 {
|
|
compatible = "sil,sii9022-cpi", "sil,sii9022";
|
|
reg = <0x60>;
|
|
};
|
|
};
|
|
|
|
rtc@17000 {
|
|
compatible = "arm,pl031", "arm,primecell";
|
|
reg = <0x17000 0x1000>;
|
|
interrupts = <4>;
|
|
clocks = <&smbclk>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
compact-flash@1a000 {
|
|
compatible = "arm,vexpress-cf", "ata-generic";
|
|
reg = <0x1a000 0x100
|
|
0x1a100 0xf00>;
|
|
reg-shift = <2>;
|
|
};
|
|
|
|
clcd@1f000 {
|
|
compatible = "arm,pl111", "arm,primecell";
|
|
reg = <0x1f000 0x1000>;
|
|
interrupt-names = "combined";
|
|
interrupts = <14>;
|
|
clocks = <&v2m_oscclk1>, <&smbclk>;
|
|
clock-names = "clcdclk", "apb_pclk";
|
|
memory-region = <&v2m_video_ram>;
|
|
max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
|
|
|
|
port {
|
|
v2m_clcd_pads: endpoint {
|
|
remote-endpoint = <&v2m_clcd_panel>;
|
|
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
|
};
|
|
};
|
|
|
|
panel {
|
|
compatible = "panel-dpi";
|
|
|
|
port {
|
|
v2m_clcd_panel: endpoint {
|
|
remote-endpoint = <&v2m_clcd_pads>;
|
|
};
|
|
};
|
|
|
|
panel-timing {
|
|
clock-frequency = <25175000>;
|
|
hactive = <640>;
|
|
hback-porch = <40>;
|
|
hfront-porch = <24>;
|
|
hsync-len = <96>;
|
|
vactive = <480>;
|
|
vback-porch = <32>;
|
|
vfront-porch = <11>;
|
|
vsync-len = <2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
v2m_fixed_3v3: fixedregulator@0 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "3V3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
v2m_clk24mhz: clk24mhz {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <24000000>;
|
|
clock-output-names = "v2m:clk24mhz";
|
|
};
|
|
|
|
v2m_refclk1mhz: refclk1mhz {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <1000000>;
|
|
clock-output-names = "v2m:refclk1mhz";
|
|
};
|
|
|
|
v2m_refclk32khz: refclk32khz {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
clock-output-names = "v2m:refclk32khz";
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
user@1 {
|
|
label = "v2m:green:user1";
|
|
gpios = <&v2m_led_gpios 0 0>;
|
|
linux,default-trigger = "heartbeat";
|
|
};
|
|
|
|
user@2 {
|
|
label = "v2m:green:user2";
|
|
gpios = <&v2m_led_gpios 1 0>;
|
|
linux,default-trigger = "mmc0";
|
|
};
|
|
|
|
user@3 {
|
|
label = "v2m:green:user3";
|
|
gpios = <&v2m_led_gpios 2 0>;
|
|
linux,default-trigger = "cpu0";
|
|
};
|
|
|
|
user@4 {
|
|
label = "v2m:green:user4";
|
|
gpios = <&v2m_led_gpios 3 0>;
|
|
linux,default-trigger = "cpu1";
|
|
};
|
|
|
|
user@5 {
|
|
label = "v2m:green:user5";
|
|
gpios = <&v2m_led_gpios 4 0>;
|
|
linux,default-trigger = "cpu2";
|
|
};
|
|
|
|
user@6 {
|
|
label = "v2m:green:user6";
|
|
gpios = <&v2m_led_gpios 5 0>;
|
|
linux,default-trigger = "cpu3";
|
|
};
|
|
|
|
user@7 {
|
|
label = "v2m:green:user7";
|
|
gpios = <&v2m_led_gpios 6 0>;
|
|
linux,default-trigger = "cpu4";
|
|
};
|
|
|
|
user@8 {
|
|
label = "v2m:green:user8";
|
|
gpios = <&v2m_led_gpios 7 0>;
|
|
linux,default-trigger = "cpu5";
|
|
};
|
|
};
|
|
|
|
mcc {
|
|
compatible = "arm,vexpress,config-bus";
|
|
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
|
|
|
osc@0 {
|
|
/* MCC static memory clock */
|
|
compatible = "arm,vexpress-osc";
|
|
arm,vexpress-sysreg,func = <1 0>;
|
|
freq-range = <25000000 60000000>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "v2m:oscclk0";
|
|
};
|
|
|
|
v2m_oscclk1: osc@1 {
|
|
/* CLCD clock */
|
|
compatible = "arm,vexpress-osc";
|
|
arm,vexpress-sysreg,func = <1 1>;
|
|
freq-range = <23750000 65000000>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "v2m:oscclk1";
|
|
};
|
|
|
|
v2m_oscclk2: osc@2 {
|
|
/* IO FPGA peripheral clock */
|
|
compatible = "arm,vexpress-osc";
|
|
arm,vexpress-sysreg,func = <1 2>;
|
|
freq-range = <24000000 24000000>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "v2m:oscclk2";
|
|
};
|
|
|
|
volt@0 {
|
|
/* Logic level voltage */
|
|
compatible = "arm,vexpress-volt";
|
|
arm,vexpress-sysreg,func = <2 0>;
|
|
regulator-name = "VIO";
|
|
regulator-always-on;
|
|
label = "VIO";
|
|
};
|
|
|
|
temp@0 {
|
|
/* MCC internal operating temperature */
|
|
compatible = "arm,vexpress-temp";
|
|
arm,vexpress-sysreg,func = <4 0>;
|
|
label = "MCC";
|
|
};
|
|
|
|
reset@0 {
|
|
compatible = "arm,vexpress-reset";
|
|
arm,vexpress-sysreg,func = <5 0>;
|
|
};
|
|
|
|
muxfpga@0 {
|
|
compatible = "arm,vexpress-muxfpga";
|
|
arm,vexpress-sysreg,func = <7 0>;
|
|
};
|
|
|
|
shutdown@0 {
|
|
compatible = "arm,vexpress-shutdown";
|
|
arm,vexpress-sysreg,func = <8 0>;
|
|
};
|
|
|
|
reboot@0 {
|
|
compatible = "arm,vexpress-reboot";
|
|
arm,vexpress-sysreg,func = <9 0>;
|
|
};
|
|
|
|
dvimode@0 {
|
|
compatible = "arm,vexpress-dvimode";
|
|
arm,vexpress-sysreg,func = <11 0>;
|
|
};
|
|
};
|
|
};
|