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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8e6ebfaa9b
remove tps65217.dtsi and adapt all boards, which used it. Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Keerthy <j-keerthy@ti.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
250 lines
6.7 KiB
Plaintext
250 lines
6.7 KiB
Plaintext
/*
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* Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
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* Author: Rostislav Lisovy <lisovy@jablotron.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "am33xx.dtsi"
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/ {
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model = "Grinn AM335x ChiliSOM";
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compatible = "grinn,am335x-chilisom", "ti,am33xx";
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cpus {
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cpu@0 {
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cpu0-supply = <&dcdc2_reg>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x20000000>; /* 512 MB */
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};
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};
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&am33xx_pinmux {
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pinctrl-names = "default";
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i2c0_pins: pinmux_i2c0_pins {
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pinctrl-single,pins = <
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AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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>;
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};
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
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AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
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>;
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};
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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/* Slave 1 */
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AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
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AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
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AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
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AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
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AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
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AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
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AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
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AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */
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>;
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};
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cpsw_sleep: cpsw_sleep {
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pinctrl-single,pins = <
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/* Slave 1 reset value */
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AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
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>;
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};
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davinci_mdio_default: davinci_mdio_default {
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pinctrl-single,pins = <
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/* mdio_data.mdio_data */
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AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
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/* mdio_clk.mdio_clk */
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AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
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>;
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};
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davinci_mdio_sleep: davinci_mdio_sleep {
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pinctrl-single,pins = <
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/* MDIO reset value */
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AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
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>;
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};
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nandflash_pins: nandflash_pins {
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pinctrl-single,pins = <
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AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
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AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
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AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
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AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
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AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
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AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
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AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
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AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
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AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
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AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
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AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
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AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
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AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */
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AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
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>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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clock-frequency = <400000>;
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tps: tps@24 {
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reg = <0x24>;
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};
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};
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&tps {
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compatible = "ti,tps65217";
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regulators {
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#address-cells = <1>;
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#size-cells = <0>;
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dcdc1_reg: regulator@0 {
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reg = <0>;
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regulator-name = "vdds_dpr";
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regulator-always-on;
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};
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dcdc2_reg: regulator@1 {
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reg = <1>;
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/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
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regulator-name = "vdd_mpu";
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regulator-min-microvolt = <925000>;
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regulator-max-microvolt = <1325000>;
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regulator-boot-on;
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regulator-always-on;
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};
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dcdc3_reg: regulator@2 {
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reg = <2>;
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/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
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regulator-name = "vdd_core";
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regulator-min-microvolt = <925000>;
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regulator-max-microvolt = <1150000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1_reg: regulator@3 {
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reg = <3>;
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regulator-name = "vio,vrtc,vdds";
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2_reg: regulator@4 {
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reg = <4>;
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regulator-name = "vdd_3v3aux";
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3_reg: regulator@5 {
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reg = <5>;
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regulator-name = "vdd_1v8";
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4_reg: regulator@6 {
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reg = <6>;
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regulator-name = "vdd_3v3d";
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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/* Ethernet MAC */
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&mac {
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slaves = <1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&cpsw_default>;
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pinctrl-1 = <&cpsw_sleep>;
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status = "okay";
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};
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&davinci_mdio {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&davinci_mdio_default>;
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pinctrl-1 = <&davinci_mdio_sleep>;
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status = "okay";
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};
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/* NAND Flash */
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&elm {
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status = "okay";
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};
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&gpmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&nandflash_pins>;
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ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
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nand@0,0 {
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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gpmc,device-width = <1>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <44>;
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gpmc,cs-wr-off-ns = <44>;
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gpmc,adv-on-ns = <6>;
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gpmc,adv-rd-off-ns = <34>;
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gpmc,adv-wr-off-ns = <44>;
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gpmc,we-on-ns = <0>;
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gpmc,we-off-ns = <40>;
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gpmc,oe-on-ns = <0>;
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gpmc,oe-off-ns = <54>;
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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};
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};
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