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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d6a99de704
- enable ARCH_HAS_BANDGAP for exynos SoCs - always enable PM domains for exynos4x12 - skip C1 cpuidle state for exynos5440 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJSHMs0AAoJEA0Cl+kVi2xqR1sQAJEhlsqPuEH1SPA/FqI8JT6P feZUcNyVsv5Y5NreVvgV62178T5LAUR2nypoNLfZaHBFHqggW0yam8mimyKvF5uF A6Sw4585OV4Obj5O5eviFfwkCWjNgF/o0hpX6/l85/7tbHxSFPnHGjKPvF6b4F4Q JiFYW0z6O7puQHu8ttj11vYxVz3dEugzwvhtVbPicXijpgiLE7K8gtpGNvWLy38y zqCUAv/Ovxk7b1PZmkFsfrceI8vjiRe1O3XU/mwN2YbbWT/B/Q/N5+dXlg2mZWPj fAge0NW59iU4uKIo1OQIH4355XXT7dyecqDdCRe8bmQgN62/cBw3750xyli2j9Bh BtzfYqVALLr/9Jd1DRaMSCF0UK0mJ12grwgU+qOsB7xYYnsA8irbg2zJHJRtdYE0 k9sZRAjlVnshkosyzHcPTOfKk89sL8D/xXq4i82ChYHGHA/V/o4VypKVIn4BGXrL s4ScCCJ2OG0cVLLxBe+GOfYyu1lENtDeofnYs6/m/qhvA1JaGdVzyy2kdONfsz0T UCHy4ym+oj/5ZI6lhJWt2p/wZOOal+f2u+l3wvoGNmZn/GoCYd0qIS/bTjWdwEYt ITzfVOS3wZoY6LTHSm7+G6KMZTR1J+9JeVoDUzyP2HNsUVnAB7mSZL8eMLiEKzlh CTOfpUZmBKdWmm/JfJGP =JARn -----END PGP SIGNATURE----- Merge tag 'samsung-mach-exynos-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into late/all update mach-exynos v2 for v3.12 - enable ARCH_HAS_BANDGAP for exynos SoCs - always enable PM domains for exynos4x12 - skip C1 cpuidle state for exynos5440 * tag 'samsung-mach-exynos-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Skip C1 cpuidle state for exynos5440 ARM: EXYNOS: always enable PM domains support for EXYNOS4X12 ARM: EXYNOS: enable ARCH_HAS_BANDGAP Signed-off-by: Olof Johansson <olof@lixom.net>
230 lines
5.6 KiB
C
230 lines
5.6 KiB
C
/* linux/arch/arm/mach-exynos4/cpuidle.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/cpuidle.h>
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#include <linux/cpu_pm.h>
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#include <linux/io.h>
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#include <linux/export.h>
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#include <linux/time.h>
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#include <asm/proc-fns.h>
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#include <asm/smp_scu.h>
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#include <asm/suspend.h>
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#include <asm/unified.h>
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#include <asm/cpuidle.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-pmu.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include "common.h"
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#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
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S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
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(S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
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#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
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S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
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(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
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#define S5P_CHECK_AFTR 0xFCBA0D10
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static int exynos4_enter_lowpower(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index);
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static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
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static struct cpuidle_driver exynos4_idle_driver = {
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.name = "exynos4_idle",
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.owner = THIS_MODULE,
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.states = {
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[0] = ARM_CPUIDLE_WFI_STATE,
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[1] = {
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.enter = exynos4_enter_lowpower,
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.exit_latency = 300,
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.target_residency = 100000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C1",
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.desc = "ARM power down",
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},
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},
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.state_count = 2,
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.safe_state_index = 0,
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};
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/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
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static void exynos4_set_wakeupmask(void)
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{
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__raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
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}
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static unsigned int g_pwr_ctrl, g_diag_reg;
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static void save_cpu_arch_register(void)
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{
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/*read power control register*/
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asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
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/*read diagnostic register*/
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asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
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return;
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}
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static void restore_cpu_arch_register(void)
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{
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/*write power control register*/
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asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
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/*write diagnostic register*/
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asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
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return;
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}
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static int idle_finisher(unsigned long flags)
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{
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cpu_do_idle();
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return 1;
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}
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static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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unsigned long tmp;
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exynos4_set_wakeupmask();
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/* Set value of power down register for aftr mode */
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exynos_sys_powerdown_conf(SYS_AFTR);
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__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
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__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
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save_cpu_arch_register();
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/* Setting Central Sequence Register for power down mode */
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tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
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tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
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__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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cpu_pm_enter();
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cpu_suspend(0, idle_finisher);
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#ifdef CONFIG_SMP
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if (!soc_is_exynos5250())
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scu_enable(S5P_VA_SCU);
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#endif
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cpu_pm_exit();
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restore_cpu_arch_register();
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/*
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* If PMU failed while entering sleep mode, WFI will be
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* ignored by PMU and then exiting cpu_do_idle().
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* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
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* in this situation.
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*/
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tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
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if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
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tmp |= S5P_CENTRAL_LOWPWR_CFG;
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__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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}
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/* Clear wakeup state register */
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__raw_writel(0x0, S5P_WAKEUP_STAT);
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return index;
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}
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static int exynos4_enter_lowpower(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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int new_index = index;
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/* This mode only can be entered when other core's are offline */
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if (num_online_cpus() > 1)
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new_index = drv->safe_state_index;
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if (new_index == 0)
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return arm_cpuidle_simple_enter(dev, drv, new_index);
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else
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return exynos4_enter_core0_aftr(dev, drv, new_index);
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}
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static void __init exynos5_core_down_clk(void)
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{
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unsigned int tmp;
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/*
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* Enable arm clock down (in idle) and set arm divider
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* ratios in WFI/WFE state.
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*/
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tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
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PWR_CTRL1_CORE1_DOWN_RATIO | \
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PWR_CTRL1_DIV2_DOWN_EN | \
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PWR_CTRL1_DIV1_DOWN_EN | \
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PWR_CTRL1_USE_CORE1_WFE | \
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PWR_CTRL1_USE_CORE0_WFE | \
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PWR_CTRL1_USE_CORE1_WFI | \
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PWR_CTRL1_USE_CORE0_WFI;
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__raw_writel(tmp, EXYNOS5_PWR_CTRL1);
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/*
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* Enable arm clock up (on exiting idle). Set arm divider
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* ratios when not in idle along with the standby duration
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* ratios.
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*/
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tmp = PWR_CTRL2_DIV2_UP_EN | \
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PWR_CTRL2_DIV1_UP_EN | \
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PWR_CTRL2_DUR_STANDBY2_VAL | \
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PWR_CTRL2_DUR_STANDBY1_VAL | \
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PWR_CTRL2_CORE2_UP_RATIO | \
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PWR_CTRL2_CORE1_UP_RATIO;
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__raw_writel(tmp, EXYNOS5_PWR_CTRL2);
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}
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static int __init exynos4_init_cpuidle(void)
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{
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int cpu_id, ret;
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struct cpuidle_device *device;
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if (soc_is_exynos5250())
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exynos5_core_down_clk();
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if (soc_is_exynos5440())
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exynos4_idle_driver.state_count = 1;
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ret = cpuidle_register_driver(&exynos4_idle_driver);
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if (ret) {
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printk(KERN_ERR "CPUidle failed to register driver\n");
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return ret;
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}
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for_each_online_cpu(cpu_id) {
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device = &per_cpu(exynos4_cpuidle_device, cpu_id);
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device->cpu = cpu_id;
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/* Support IDLE only */
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if (cpu_id != 0)
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device->state_count = 1;
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ret = cpuidle_register_device(device);
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if (ret) {
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printk(KERN_ERR "CPUidle register device failed\n");
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return ret;
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}
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}
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return 0;
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}
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device_initcall(exynos4_init_cpuidle);
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