mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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368b8e2523
Convert the zynq platform to be using the gic_handle_irq function as its primary interrupt handler. Acked-by: John Linn <john.linn@xilinx.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
120 lines
2.8 KiB
C
120 lines
2.8 KiB
C
/*
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* This file contains common code that is intended to be used across
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* boards so that it's not replicated.
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*
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* Copyright (C) 2011 Xilinx
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/cpumask.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/of.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach-types.h>
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#include <asm/page.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <mach/zynq_soc.h>
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#include <mach/clkdev.h>
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#include "common.h"
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static struct of_device_id zynq_of_bus_ids[] __initdata = {
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{ .compatible = "simple-bus", },
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{}
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};
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/**
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* xilinx_init_machine() - System specific initialization, intended to be
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* called from board specific initialization.
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*/
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static void __init xilinx_init_machine(void)
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{
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#ifdef CONFIG_CACHE_L2X0
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/*
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* 64KB way size, 8-way associativity, parity disabled
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*/
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l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF);
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#endif
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of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL);
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}
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/**
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* xilinx_irq_init() - Interrupt controller initialization for the GIC.
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*/
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static void __init xilinx_irq_init(void)
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{
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gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE);
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}
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/* The minimum devices needed to be mapped before the VM system is up and
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* running include the GIC, UART and Timer Counter.
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*/
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static struct map_desc io_desc[] __initdata = {
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{
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.virtual = TTC0_VIRT,
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.pfn = __phys_to_pfn(TTC0_PHYS),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = SCU_PERIPH_VIRT,
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.pfn = __phys_to_pfn(SCU_PERIPH_PHYS),
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.length = SZ_8K,
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.type = MT_DEVICE,
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}, {
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.virtual = PL310_L2CC_VIRT,
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.pfn = __phys_to_pfn(PL310_L2CC_PHYS),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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#ifdef CONFIG_DEBUG_LL
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{
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.virtual = UART0_VIRT,
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.pfn = __phys_to_pfn(UART0_PHYS),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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#endif
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};
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/**
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* xilinx_map_io() - Create memory mappings needed for early I/O.
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*/
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static void __init xilinx_map_io(void)
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{
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iotable_init(io_desc, ARRAY_SIZE(io_desc));
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}
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static const char *xilinx_dt_match[] = {
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"xlnx,zynq-ep107",
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NULL
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};
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MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
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.map_io = xilinx_map_io,
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.init_irq = xilinx_irq_init,
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.handle_irq = gic_handle_irq,
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.init_machine = xilinx_init_machine,
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.timer = &xttcpss_sys_timer,
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.dt_compat = xilinx_dt_match,
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MACHINE_END
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