mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 13:20:23 +07:00
51a43be9fa
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
495 lines
11 KiB
C
495 lines
11 KiB
C
/*
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* drivers/clk/at91/clk-slow.c
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*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/sched.h>
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#include <linux/wait.h>
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#include "pmc.h"
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#include "sckc.h"
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#define SLOW_CLOCK_FREQ 32768
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#define SLOWCK_SW_CYCLES 5
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#define SLOWCK_SW_TIME_USEC ((SLOWCK_SW_CYCLES * USEC_PER_SEC) / \
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SLOW_CLOCK_FREQ)
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#define AT91_SCKC_CR 0x00
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#define AT91_SCKC_RCEN (1 << 0)
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#define AT91_SCKC_OSC32EN (1 << 1)
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#define AT91_SCKC_OSC32BYP (1 << 2)
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#define AT91_SCKC_OSCSEL (1 << 3)
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struct clk_slow_osc {
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struct clk_hw hw;
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void __iomem *sckcr;
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unsigned long startup_usec;
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};
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#define to_clk_slow_osc(hw) container_of(hw, struct clk_slow_osc, hw)
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struct clk_slow_rc_osc {
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struct clk_hw hw;
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void __iomem *sckcr;
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unsigned long frequency;
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unsigned long accuracy;
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unsigned long startup_usec;
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};
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#define to_clk_slow_rc_osc(hw) container_of(hw, struct clk_slow_rc_osc, hw)
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struct clk_sam9260_slow {
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struct clk_hw hw;
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struct at91_pmc *pmc;
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};
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#define to_clk_sam9260_slow(hw) container_of(hw, struct clk_sam9260_slow, hw)
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struct clk_sam9x5_slow {
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struct clk_hw hw;
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void __iomem *sckcr;
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u8 parent;
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};
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#define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw)
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static struct clk *slow_clk;
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static int clk_slow_osc_prepare(struct clk_hw *hw)
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{
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struct clk_slow_osc *osc = to_clk_slow_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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u32 tmp = readl(sckcr);
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if (tmp & AT91_SCKC_OSC32BYP)
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return 0;
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writel(tmp | AT91_SCKC_OSC32EN, sckcr);
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usleep_range(osc->startup_usec, osc->startup_usec + 1);
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return 0;
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}
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static void clk_slow_osc_unprepare(struct clk_hw *hw)
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{
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struct clk_slow_osc *osc = to_clk_slow_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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u32 tmp = readl(sckcr);
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if (tmp & AT91_SCKC_OSC32BYP)
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return;
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writel(tmp & ~AT91_SCKC_OSC32EN, sckcr);
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}
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static int clk_slow_osc_is_prepared(struct clk_hw *hw)
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{
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struct clk_slow_osc *osc = to_clk_slow_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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u32 tmp = readl(sckcr);
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if (tmp & AT91_SCKC_OSC32BYP)
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return 1;
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return !!(tmp & AT91_SCKC_OSC32EN);
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}
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static const struct clk_ops slow_osc_ops = {
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.prepare = clk_slow_osc_prepare,
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.unprepare = clk_slow_osc_unprepare,
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.is_prepared = clk_slow_osc_is_prepared,
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};
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static struct clk * __init
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at91_clk_register_slow_osc(void __iomem *sckcr,
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const char *name,
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const char *parent_name,
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unsigned long startup,
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bool bypass)
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{
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struct clk_slow_osc *osc;
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struct clk *clk = NULL;
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struct clk_init_data init;
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if (!sckcr || !name || !parent_name)
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return ERR_PTR(-EINVAL);
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osc = kzalloc(sizeof(*osc), GFP_KERNEL);
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if (!osc)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &slow_osc_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = CLK_IGNORE_UNUSED;
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osc->hw.init = &init;
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osc->sckcr = sckcr;
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osc->startup_usec = startup;
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if (bypass)
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writel((readl(sckcr) & ~AT91_SCKC_OSC32EN) | AT91_SCKC_OSC32BYP,
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sckcr);
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clk = clk_register(NULL, &osc->hw);
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if (IS_ERR(clk))
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kfree(osc);
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return clk;
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}
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void __init of_at91sam9x5_clk_slow_osc_setup(struct device_node *np,
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void __iomem *sckcr)
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{
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struct clk *clk;
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const char *parent_name;
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const char *name = np->name;
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u32 startup;
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bool bypass;
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parent_name = of_clk_get_parent_name(np, 0);
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of_property_read_string(np, "clock-output-names", &name);
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of_property_read_u32(np, "atmel,startup-time-usec", &startup);
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bypass = of_property_read_bool(np, "atmel,osc-bypass");
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clk = at91_clk_register_slow_osc(sckcr, name, parent_name, startup,
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bypass);
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if (IS_ERR(clk))
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return;
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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}
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static unsigned long clk_slow_rc_osc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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return osc->frequency;
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}
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static unsigned long clk_slow_rc_osc_recalc_accuracy(struct clk_hw *hw,
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unsigned long parent_acc)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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return osc->accuracy;
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}
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static int clk_slow_rc_osc_prepare(struct clk_hw *hw)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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writel(readl(sckcr) | AT91_SCKC_RCEN, sckcr);
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usleep_range(osc->startup_usec, osc->startup_usec + 1);
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return 0;
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}
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static void clk_slow_rc_osc_unprepare(struct clk_hw *hw)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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void __iomem *sckcr = osc->sckcr;
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writel(readl(sckcr) & ~AT91_SCKC_RCEN, sckcr);
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}
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static int clk_slow_rc_osc_is_prepared(struct clk_hw *hw)
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{
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struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
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return !!(readl(osc->sckcr) & AT91_SCKC_RCEN);
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}
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static const struct clk_ops slow_rc_osc_ops = {
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.prepare = clk_slow_rc_osc_prepare,
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.unprepare = clk_slow_rc_osc_unprepare,
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.is_prepared = clk_slow_rc_osc_is_prepared,
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.recalc_rate = clk_slow_rc_osc_recalc_rate,
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.recalc_accuracy = clk_slow_rc_osc_recalc_accuracy,
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};
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static struct clk * __init
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at91_clk_register_slow_rc_osc(void __iomem *sckcr,
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const char *name,
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unsigned long frequency,
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unsigned long accuracy,
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unsigned long startup)
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{
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struct clk_slow_rc_osc *osc;
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struct clk *clk = NULL;
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struct clk_init_data init;
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if (!sckcr || !name)
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return ERR_PTR(-EINVAL);
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osc = kzalloc(sizeof(*osc), GFP_KERNEL);
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if (!osc)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &slow_rc_osc_ops;
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init.parent_names = NULL;
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init.num_parents = 0;
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init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED;
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osc->hw.init = &init;
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osc->sckcr = sckcr;
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osc->frequency = frequency;
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osc->accuracy = accuracy;
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osc->startup_usec = startup;
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clk = clk_register(NULL, &osc->hw);
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if (IS_ERR(clk))
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kfree(osc);
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return clk;
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}
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void __init of_at91sam9x5_clk_slow_rc_osc_setup(struct device_node *np,
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void __iomem *sckcr)
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{
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struct clk *clk;
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u32 frequency = 0;
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u32 accuracy = 0;
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u32 startup = 0;
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const char *name = np->name;
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of_property_read_string(np, "clock-output-names", &name);
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of_property_read_u32(np, "clock-frequency", &frequency);
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of_property_read_u32(np, "clock-accuracy", &accuracy);
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of_property_read_u32(np, "atmel,startup-time-usec", &startup);
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clk = at91_clk_register_slow_rc_osc(sckcr, name, frequency, accuracy,
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startup);
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if (IS_ERR(clk))
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return;
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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}
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static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
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void __iomem *sckcr = slowck->sckcr;
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u32 tmp;
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if (index > 1)
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return -EINVAL;
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tmp = readl(sckcr);
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if ((!index && !(tmp & AT91_SCKC_OSCSEL)) ||
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(index && (tmp & AT91_SCKC_OSCSEL)))
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return 0;
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if (index)
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tmp |= AT91_SCKC_OSCSEL;
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else
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tmp &= ~AT91_SCKC_OSCSEL;
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writel(tmp, sckcr);
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usleep_range(SLOWCK_SW_TIME_USEC, SLOWCK_SW_TIME_USEC + 1);
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return 0;
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}
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static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw)
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{
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struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
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return !!(readl(slowck->sckcr) & AT91_SCKC_OSCSEL);
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}
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static const struct clk_ops sam9x5_slow_ops = {
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.set_parent = clk_sam9x5_slow_set_parent,
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.get_parent = clk_sam9x5_slow_get_parent,
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};
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static struct clk * __init
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at91_clk_register_sam9x5_slow(void __iomem *sckcr,
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const char *name,
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const char **parent_names,
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int num_parents)
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{
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struct clk_sam9x5_slow *slowck;
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struct clk *clk = NULL;
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struct clk_init_data init;
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if (!sckcr || !name || !parent_names || !num_parents)
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return ERR_PTR(-EINVAL);
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slowck = kzalloc(sizeof(*slowck), GFP_KERNEL);
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if (!slowck)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &sam9x5_slow_ops;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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init.flags = 0;
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slowck->hw.init = &init;
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slowck->sckcr = sckcr;
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slowck->parent = !!(readl(sckcr) & AT91_SCKC_OSCSEL);
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clk = clk_register(NULL, &slowck->hw);
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if (IS_ERR(clk))
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kfree(slowck);
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else
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slow_clk = clk;
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return clk;
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}
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void __init of_at91sam9x5_clk_slow_setup(struct device_node *np,
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void __iomem *sckcr)
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{
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struct clk *clk;
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const char *parent_names[2];
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int num_parents;
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const char *name = np->name;
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int i;
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num_parents = of_clk_get_parent_count(np);
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if (num_parents <= 0 || num_parents > 2)
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return;
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for (i = 0; i < num_parents; ++i) {
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parent_names[i] = of_clk_get_parent_name(np, i);
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if (!parent_names[i])
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return;
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}
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of_property_read_string(np, "clock-output-names", &name);
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clk = at91_clk_register_sam9x5_slow(sckcr, name, parent_names,
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num_parents);
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if (IS_ERR(clk))
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return;
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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}
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static u8 clk_sam9260_slow_get_parent(struct clk_hw *hw)
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{
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struct clk_sam9260_slow *slowck = to_clk_sam9260_slow(hw);
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return !!(pmc_read(slowck->pmc, AT91_PMC_SR) & AT91_PMC_OSCSEL);
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}
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static const struct clk_ops sam9260_slow_ops = {
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.get_parent = clk_sam9260_slow_get_parent,
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};
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static struct clk * __init
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at91_clk_register_sam9260_slow(struct at91_pmc *pmc,
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const char *name,
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const char **parent_names,
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int num_parents)
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{
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struct clk_sam9260_slow *slowck;
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struct clk *clk = NULL;
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struct clk_init_data init;
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if (!pmc || !name)
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return ERR_PTR(-EINVAL);
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if (!parent_names || !num_parents)
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return ERR_PTR(-EINVAL);
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slowck = kzalloc(sizeof(*slowck), GFP_KERNEL);
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if (!slowck)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &sam9260_slow_ops;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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init.flags = 0;
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slowck->hw.init = &init;
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slowck->pmc = pmc;
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clk = clk_register(NULL, &slowck->hw);
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if (IS_ERR(clk))
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kfree(slowck);
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else
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slow_clk = clk;
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return clk;
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}
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void __init of_at91sam9260_clk_slow_setup(struct device_node *np,
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struct at91_pmc *pmc)
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{
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struct clk *clk;
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const char *parent_names[2];
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int num_parents;
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const char *name = np->name;
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int i;
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num_parents = of_clk_get_parent_count(np);
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if (num_parents != 2)
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return;
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for (i = 0; i < num_parents; ++i) {
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parent_names[i] = of_clk_get_parent_name(np, i);
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if (!parent_names[i])
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return;
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}
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of_property_read_string(np, "clock-output-names", &name);
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clk = at91_clk_register_sam9260_slow(pmc, name, parent_names,
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num_parents);
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if (IS_ERR(clk))
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return;
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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}
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/*
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* FIXME: All slow clk users are not properly claiming it (get + prepare +
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* enable) before using it.
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* If all users properly claiming this clock decide that they don't need it
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* anymore (or are removed), it is disabled while faulty users are still
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* requiring it, and the system hangs.
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* Prevent this clock from being disabled until all users are properly
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* requesting it.
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* Once this is done we should remove this function and the slow_clk variable.
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*/
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static int __init of_at91_clk_slow_retain(void)
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{
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if (!slow_clk)
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return 0;
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__clk_get(slow_clk);
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clk_prepare_enable(slow_clk);
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return 0;
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}
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arch_initcall(of_at91_clk_slow_retain);
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