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8b99dc0922
This patch adds the gpio-ranges property to almost all of the Qualcomm ARM platforms that utilize the pinctrl-msm framework. The gpio-ranges property is part of the gpiolib subsystem. As a result, the binding text is available in section "2.1 gpio- and pin-controller interaction" of Documentation/devicetree/bindings/gpio/gpio.txt For more information please see the patch titled: "pinctrl: msm: fix gpio-hog related boot issues" from this series. Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com> Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019] Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Tested-by: Robert Marko <robert.marko@sartura.hr> [ipq4019] Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://lore.kernel.org/r/20200108125455.308969-1-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
555 lines
14 KiB
Plaintext
555 lines
14 KiB
Plaintext
/*
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* Device Tree Source for Qualcomm MDM9615 SoC
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*
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* Copyright (C) 2016 BayLibre, SAS.
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* Author : Neil Armstrong <narmstrong@baylibre.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-mdm9615.h>
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#include <dt-bindings/reset/qcom,gcc-mdm9615.h>
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#include <dt-bindings/mfd/qcom-rpm.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Qualcomm MDM9615";
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compatible = "qcom,mdm9615";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a5";
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device_type = "cpu";
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next-level-cache = <&L2>;
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};
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};
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cpu-pmu {
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compatible = "arm,cortex-a5-pmu";
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interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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clocks {
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cxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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};
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};
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regulators {
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vsdcc_fixed: vsdcc-regulator {
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compatible = "regulator-fixed";
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regulator-name = "SDCC Power";
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regulator-min-microvolt = <2700000>;
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regulator-max-microvolt = <2700000>;
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regulator-always-on;
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};
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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L2: l2-cache@2040000 {
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compatible = "arm,pl310-cache";
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reg = <0x02040000 0x1000>;
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arm,data-latency = <2 2 0>;
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cache-unified;
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cache-level = <2>;
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};
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intc: interrupt-controller@2000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x02000000 0x1000>,
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<0x02002000 0x1000>;
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};
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timer@200a000 {
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compatible = "qcom,kpss-timer", "qcom,msm-timer";
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interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x80000>;
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};
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msmgpio: pinctrl@800000 {
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compatible = "qcom,mdm9615-pinctrl";
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gpio-controller;
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gpio-ranges = <&msmgpio 0 0 88>;
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#gpio-cells = <2>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x800000 0x4000>;
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-mdm9615";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0x900000 0x4000>;
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};
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lcc: clock-controller@28000000 {
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compatible = "qcom,lcc-mdm9615";
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reg = <0x28000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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l2cc: clock-controller@2011000 {
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compatible = "syscon";
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reg = <0x02011000 0x1000>;
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};
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rng@1a500000 {
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compatible = "qcom,prng";
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reg = <0x1a500000 0x200>;
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clocks = <&gcc PRNG_CLK>;
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clock-names = "core";
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assigned-clocks = <&gcc PRNG_CLK>;
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assigned-clock-rates = <32000000>;
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};
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gsbi2: gsbi@16100000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <2>;
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reg = <0x16100000 0x100>;
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clocks = <&gcc GSBI2_H_CLK>;
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clock-names = "iface";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gsbi2_i2c: i2c@16180000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x16180000 0x1000>;
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interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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};
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gsbi3: gsbi@16200000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <3>;
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reg = <0x16200000 0x100>;
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clocks = <&gcc GSBI3_H_CLK>;
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clock-names = "iface";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gsbi3_spi: spi@16280000 {
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compatible = "qcom,spi-qup-v1.1.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x16280000 0x1000>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <24000000>;
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clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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};
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gsbi4: gsbi@16300000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <4>;
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reg = <0x16300000 0x100>;
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clocks = <&gcc GSBI4_H_CLK>;
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clock-names = "iface";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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gsbi4_serial: serial@16340000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16340000 0x1000>,
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<0x16300000 0x1000>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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};
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gsbi5: gsbi@16400000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <5>;
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reg = <0x16400000 0x100>;
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clocks = <&gcc GSBI5_H_CLK>;
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clock-names = "iface";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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gsbi5_i2c: i2c@16480000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x16480000 0x1000>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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/* QUP clock is not initialized, set rate */
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assigned-clocks = <&gcc GSBI5_QUP_CLK>;
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assigned-clock-rates = <24000000>;
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clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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gsbi5_serial: serial@16440000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16440000 0x1000>,
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<0x16400000 0x1000>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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};
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qcom,ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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pmicintc: pmic@0 {
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compatible = "qcom,pm8018", "qcom,pm8921";
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interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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pwrkey@1c {
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compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
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reg = <0x1c>;
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interrupt-parent = <&pmicintc>;
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interrupts = <50 IRQ_TYPE_EDGE_RISING>,
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<51 IRQ_TYPE_EDGE_RISING>;
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debounce = <15625>;
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pull-up;
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};
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pmicmpp: mpp@50 {
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compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
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interrupt-parent = <&pmicintc>;
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interrupts = <24 IRQ_TYPE_NONE>,
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<25 IRQ_TYPE_NONE>,
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<26 IRQ_TYPE_NONE>,
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<27 IRQ_TYPE_NONE>,
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<28 IRQ_TYPE_NONE>,
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<29 IRQ_TYPE_NONE>;
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reg = <0x50>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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rtc@11d {
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compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
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interrupt-parent = <&pmicintc>;
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interrupts = <39 IRQ_TYPE_EDGE_RISING>;
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reg = <0x11d>;
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allow-set-time;
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};
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pmicgpio: gpio@150 {
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compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pmicgpio 0 0 6>;
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#gpio-cells = <2>;
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};
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};
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};
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sdcc1bam: dma@12182000{
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12182000 0x8000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC1_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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sdcc2bam: dma@12142000{
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12142000 0x8000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC2_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sdcc1: sdcc@12180000 {
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status = "disabled";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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reg = <0x12180000 0x2000>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <8>;
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max-frequency = <48000000>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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vmmc-supply = <&vsdcc_fixed>;
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dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
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dma-names = "tx", "rx";
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assigned-clocks = <&gcc SDC1_CLK>;
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assigned-clock-rates = <400000>;
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};
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sdcc2: sdcc@12140000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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status = "disabled";
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reg = <0x12140000 0x2000>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <4>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <48000000>;
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no-1-8-v;
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vmmc-supply = <&vsdcc_fixed>;
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dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
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dma-names = "tx", "rx";
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assigned-clocks = <&gcc SDC2_CLK>;
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assigned-clock-rates = <400000>;
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};
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};
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tcsr: syscon@1a400000 {
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compatible = "qcom,tcsr-mdm9615", "syscon";
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reg = <0x1a400000 0x100>;
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};
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rpm: rpm@108000 {
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compatible = "qcom,rpm-mdm9615";
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reg = <0x108000 0x1000>;
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qcom,ipc = <&l2cc 0x8 2>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "ack", "err", "wakeup";
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regulators {
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compatible = "qcom,rpm-pm8018-regulators";
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vin_lvs1-supply = <&pm8018_s3>;
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vdd_l7-supply = <&pm8018_s4>;
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vdd_l8-supply = <&pm8018_s3>;
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vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
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/* Buck SMPS */
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pm8018_s1: s1 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1150000>;
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qcom,switch-mode-frequency = <1600000>;
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bias-pull-down;
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};
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pm8018_s2: s2 {
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regulator-min-microvolt = <1225000>;
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regulator-max-microvolt = <1300000>;
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qcom,switch-mode-frequency = <1600000>;
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bias-pull-down;
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};
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pm8018_s3: s3 {
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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qcom,switch-mode-frequency = <1600000>;
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bias-pull-down;
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};
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pm8018_s4: s4 {
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regulator-min-microvolt = <2100000>;
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regulator-max-microvolt = <2200000>;
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qcom,switch-mode-frequency = <1600000>;
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bias-pull-down;
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};
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pm8018_s5: s5 {
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regulator-always-on;
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
|
|
qcom,switch-mode-frequency = <1600000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
/* PMOS LDO */
|
|
pm8018_l2: l2 {
|
|
regulator-always-on;
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
pm8018_l3: l3 {
|
|
regulator-always-on;
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
pm8018_l4: l4 {
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
pm8018_l5: l5 {
|
|
regulator-min-microvolt = <2850000>;
|
|
regulator-max-microvolt = <2850000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
pm8018_l6: l6 {
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <2850000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
pm8018_l7: l7 {
|
|
regulator-min-microvolt = <1850000>;
|
|
regulator-max-microvolt = <1900000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
pm8018_l8: l8 {
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
pm8018_l9: l9 {
|
|
regulator-min-microvolt = <750000>;
|
|
regulator-max-microvolt = <1150000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
pm8018_l10: l10 {
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
pm8018_l11: l11 {
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
pm8018_l12: l12 {
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
pm8018_l13: l13 {
|
|
regulator-min-microvolt = <1850000>;
|
|
regulator-max-microvolt = <2950000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
pm8018_l14: l14 {
|
|
regulator-min-microvolt = <2850000>;
|
|
regulator-max-microvolt = <2850000>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
/* Low Voltage Switch */
|
|
pm8018_lvs1: lvs1 {
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|