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701016c0cb
This patch add pinctrl support to ST SoCs. About hardware: ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle pin configurations. Each multi-function pin is controlled, driven and routed through the PIO multiplexing block. Each pin supports GPIO functionality (ALT0) and multiple alternate functions(ALT1 - ALTx) that directly connect the pin to different hardware blocks. When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO block. Otherwise the PIO multiplexing block configures these parameters and retiming the signal. About driver: This pinctrl driver manages both PIO and PIO-mux block using pinctrl, pinconf, pinmux, gpio subsystems. All the pinctrl related config information can only come from device trees. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mark Brown <broonie@linaro.org>
111 lines
3.0 KiB
Plaintext
111 lines
3.0 KiB
Plaintext
*ST pin controller.
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Each multi-function pin is controlled, driven and routed through the
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PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
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and multiple alternate functions(ALT1 - ALTx) that directly connect
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the pin to different hardware blocks.
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When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
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Pull Up (PU) are driven by the related PIO block.
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ST pinctrl driver controls PIO multiplexing block and also interacts with
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gpio driver to configure a pin.
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Required properties: (PIO multiplexing block)
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- compatible : should be "st,<SOC>-<pio-block>-pinctrl"
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like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
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- gpio-controller : Indicates this device is a GPIO controller
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- #gpio-cells : Should be one. The first cell is the pin number.
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- st,retime-pin-mask : Should be mask to specify which pins can be retimed.
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If the property is not present, it is assumed that all the pins in the
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bank are capable of retiming. Retiming is mainly used to improve the
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IO timing margins of external synchronous interfaces.
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- st,bank-name : Should be a name string for this bank as
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specified in datasheet.
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- st,syscfg : Should be a phandle of the syscfg node.
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Example:
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pin-controller-sbc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stih415-sbc-pinctrl";
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st,syscfg = <&syscfg_sbc>;
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ranges = <0 0xfe610000 0x5000>;
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PIO0: gpio@fe610000 {
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gpio-controller;
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#gpio-cells = <1>;
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reg = <0 0x100>;
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st,bank-name = "PIO0";
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};
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...
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pin-functions nodes follow...
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};
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Contents of function subnode node:
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----------------------
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Required properties for pin configuration node:
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- st,pins : Child node with list of pins with configuration.
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Below is the format of how each pin conf should look like.
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<bank offset mux mode rt_type rt_delay rt_clk>
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Every PIO is represented with 4-7 parameters depending on retime configuration.
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Each parameter is explained as below.
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-bank : Should be bank phandle to which this PIO belongs.
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-offset : Offset in the PIO bank.
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-mux : Should be alternate function number associated this pin.
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Use same numbers from datasheet.
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-mode :pin configuration is selected from one of the below values.
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IN
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IN_PU
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OUT
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BIDIR
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BIDIR_PU
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-rt_type Retiming Configuration for the pin.
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Possible retime configuration are:
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------- -------------
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value args
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------- -------------
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NICLK <delay> <clk>
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ICLK_IO <delay> <clk>
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BYPASS <delay>
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DE_IO <delay> <clk>
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SE_ICLK_IO <delay> <clk>
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SE_NICLK_IO <delay> <clk>
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- delay is retime delay in pico seconds as mentioned in data sheet.
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- rt_clk :clk to be use for retime.
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Possible values are:
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CLK_A
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CLK_B
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CLK_C
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CLK_D
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Example of mmcclk pin which is a bi-direction pull pu with retime config
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as non inverted clock retimed with CLK_B and delay of 0 pico seconds:
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pin-controller {
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...
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mmc0 {
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pinctrl_mmc: mmc {
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st,pins {
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mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
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...
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};
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};
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...
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};
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};
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sdhci0:sdhci@fe810000{
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...
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mmc>;
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};
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