mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 01:13:55 +07:00
69d927bba3
Recent probing at the Linux Kernel Memory Model uncovered a 'surprise'. Strongly ordered architectures where the atomic RmW primitive implies full memory ordering and smp_mb__{before,after}_atomic() are a simple barrier() (such as x86) fail for: *x = 1; atomic_inc(u); smp_mb__after_atomic(); r0 = *y; Because, while the atomic_inc() implies memory order, it (surprisingly) does not provide a compiler barrier. This then allows the compiler to re-order like so: atomic_inc(u); *x = 1; smp_mb__after_atomic(); r0 = *y; Which the CPU is then allowed to re-order (under TSO rules) like: atomic_inc(u); r0 = *y; *x = 1; And this very much was not intended. Therefore strengthen the atomic RmW ops to include a compiler barrier. NOTE: atomic_{or,and,xor} and the bitops already had the compiler barrier. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>
268 lines
6.2 KiB
C
268 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_ATOMIC_H
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#define _ASM_X86_ATOMIC_H
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/alternative.h>
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#include <asm/cmpxchg.h>
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#include <asm/rmwcc.h>
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#include <asm/barrier.h>
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*/
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#define ATOMIC_INIT(i) { (i) }
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/**
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* arch_atomic_read - read atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically reads the value of @v.
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*/
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static __always_inline int arch_atomic_read(const atomic_t *v)
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{
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/*
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* Note for KASAN: we deliberately don't use READ_ONCE_NOCHECK() here,
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* it's non-inlined function that increases binary size and stack usage.
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*/
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return READ_ONCE((v)->counter);
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}
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/**
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* arch_atomic_set - set atomic variable
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* @v: pointer of type atomic_t
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* @i: required value
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*
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* Atomically sets the value of @v to @i.
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*/
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static __always_inline void arch_atomic_set(atomic_t *v, int i)
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{
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WRITE_ONCE(v->counter, i);
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}
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/**
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* arch_atomic_add - add integer to atomic variable
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* @i: integer value to add
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* @v: pointer of type atomic_t
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*
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* Atomically adds @i to @v.
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*/
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static __always_inline void arch_atomic_add(int i, atomic_t *v)
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{
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asm volatile(LOCK_PREFIX "addl %1,%0"
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: "+m" (v->counter)
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: "ir" (i) : "memory");
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}
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/**
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* arch_atomic_sub - subtract integer from atomic variable
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* @i: integer value to subtract
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* @v: pointer of type atomic_t
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*
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* Atomically subtracts @i from @v.
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*/
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static __always_inline void arch_atomic_sub(int i, atomic_t *v)
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{
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asm volatile(LOCK_PREFIX "subl %1,%0"
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: "+m" (v->counter)
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: "ir" (i) : "memory");
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}
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/**
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* arch_atomic_sub_and_test - subtract value from variable and test result
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* @i: integer value to subtract
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* @v: pointer of type atomic_t
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*
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* Atomically subtracts @i from @v and returns
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* true if the result is zero, or false for all
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* other cases.
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*/
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static __always_inline bool arch_atomic_sub_and_test(int i, atomic_t *v)
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{
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return GEN_BINARY_RMWcc(LOCK_PREFIX "subl", v->counter, e, "er", i);
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}
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#define arch_atomic_sub_and_test arch_atomic_sub_and_test
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/**
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* arch_atomic_inc - increment atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1.
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*/
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static __always_inline void arch_atomic_inc(atomic_t *v)
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{
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asm volatile(LOCK_PREFIX "incl %0"
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: "+m" (v->counter) :: "memory");
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}
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#define arch_atomic_inc arch_atomic_inc
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/**
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* arch_atomic_dec - decrement atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically decrements @v by 1.
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*/
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static __always_inline void arch_atomic_dec(atomic_t *v)
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{
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asm volatile(LOCK_PREFIX "decl %0"
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: "+m" (v->counter) :: "memory");
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}
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#define arch_atomic_dec arch_atomic_dec
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/**
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* arch_atomic_dec_and_test - decrement and test
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* @v: pointer of type atomic_t
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*
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* Atomically decrements @v by 1 and
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* returns true if the result is 0, or false for all other
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* cases.
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*/
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static __always_inline bool arch_atomic_dec_and_test(atomic_t *v)
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{
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return GEN_UNARY_RMWcc(LOCK_PREFIX "decl", v->counter, e);
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}
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#define arch_atomic_dec_and_test arch_atomic_dec_and_test
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/**
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* arch_atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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static __always_inline bool arch_atomic_inc_and_test(atomic_t *v)
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{
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return GEN_UNARY_RMWcc(LOCK_PREFIX "incl", v->counter, e);
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}
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#define arch_atomic_inc_and_test arch_atomic_inc_and_test
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/**
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* arch_atomic_add_negative - add and test if negative
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* @i: integer value to add
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* @v: pointer of type atomic_t
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*
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* Atomically adds @i to @v and returns true
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* if the result is negative, or false when
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* result is greater than or equal to zero.
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*/
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static __always_inline bool arch_atomic_add_negative(int i, atomic_t *v)
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{
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return GEN_BINARY_RMWcc(LOCK_PREFIX "addl", v->counter, s, "er", i);
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}
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#define arch_atomic_add_negative arch_atomic_add_negative
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/**
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* arch_atomic_add_return - add integer and return
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* @i: integer value to add
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* @v: pointer of type atomic_t
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*
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* Atomically adds @i to @v and returns @i + @v
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*/
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static __always_inline int arch_atomic_add_return(int i, atomic_t *v)
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{
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return i + xadd(&v->counter, i);
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}
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/**
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* arch_atomic_sub_return - subtract integer and return
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* @v: pointer of type atomic_t
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* @i: integer value to subtract
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*
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* Atomically subtracts @i from @v and returns @v - @i
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*/
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static __always_inline int arch_atomic_sub_return(int i, atomic_t *v)
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{
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return arch_atomic_add_return(-i, v);
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}
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static __always_inline int arch_atomic_fetch_add(int i, atomic_t *v)
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{
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return xadd(&v->counter, i);
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}
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static __always_inline int arch_atomic_fetch_sub(int i, atomic_t *v)
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{
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return xadd(&v->counter, -i);
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}
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static __always_inline int arch_atomic_cmpxchg(atomic_t *v, int old, int new)
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{
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return arch_cmpxchg(&v->counter, old, new);
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}
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#define arch_atomic_try_cmpxchg arch_atomic_try_cmpxchg
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static __always_inline bool arch_atomic_try_cmpxchg(atomic_t *v, int *old, int new)
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{
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return try_cmpxchg(&v->counter, old, new);
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}
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static inline int arch_atomic_xchg(atomic_t *v, int new)
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{
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return arch_xchg(&v->counter, new);
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}
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static inline void arch_atomic_and(int i, atomic_t *v)
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{
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asm volatile(LOCK_PREFIX "andl %1,%0"
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: "+m" (v->counter)
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: "ir" (i)
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: "memory");
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}
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static inline int arch_atomic_fetch_and(int i, atomic_t *v)
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{
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int val = arch_atomic_read(v);
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do { } while (!arch_atomic_try_cmpxchg(v, &val, val & i));
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return val;
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}
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static inline void arch_atomic_or(int i, atomic_t *v)
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{
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asm volatile(LOCK_PREFIX "orl %1,%0"
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: "+m" (v->counter)
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: "ir" (i)
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: "memory");
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}
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static inline int arch_atomic_fetch_or(int i, atomic_t *v)
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{
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int val = arch_atomic_read(v);
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do { } while (!arch_atomic_try_cmpxchg(v, &val, val | i));
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return val;
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}
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static inline void arch_atomic_xor(int i, atomic_t *v)
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{
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asm volatile(LOCK_PREFIX "xorl %1,%0"
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: "+m" (v->counter)
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: "ir" (i)
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: "memory");
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}
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static inline int arch_atomic_fetch_xor(int i, atomic_t *v)
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{
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int val = arch_atomic_read(v);
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do { } while (!arch_atomic_try_cmpxchg(v, &val, val ^ i));
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return val;
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}
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#ifdef CONFIG_X86_32
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# include <asm/atomic64_32.h>
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#else
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# include <asm/atomic64_64.h>
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#endif
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#include <asm-generic/atomic-instrumented.h>
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#endif /* _ASM_X86_ATOMIC_H */
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