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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2d4dc890b5
Mtdblock driver doesn't call flush_dcache_page for pages in request. So, this causes problems on architectures where the icache doesn't fill from the dcache or with dcache aliases. The patch fixes this. The ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE symbol was introduced to avoid pointless empty cache-thrashing loops on architectures for which flush_dcache_page() is a no-op. Every architecture was provided with this flush pages on architectires where ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE is equal 1 or do nothing otherwise. See "fix mtd_blkdevs problem with caches on some architectures" discussion on LKML for more information. Signed-off-by: Ilya Loginov <isloginov@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Peter Horton <phorton@bitbox.co.uk> Cc: "Ed L. Cashin" <ecashin@coraid.com> Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
106 lines
3.1 KiB
C
106 lines
3.1 KiB
C
/* cacheflush.h: FRV cache flushing routines
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_CACHEFLUSH_H
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#define _ASM_CACHEFLUSH_H
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/* Keep includes the same across arches. */
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#include <linux/mm.h>
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/*
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* virtually-indexed cache management (our cache is physically indexed)
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*/
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#define flush_cache_all() do {} while(0)
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#define flush_cache_mm(mm) do {} while(0)
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#define flush_cache_dup_mm(mm) do {} while(0)
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#define flush_cache_range(mm, start, end) do {} while(0)
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#define flush_cache_page(vma, vmaddr, pfn) do {} while(0)
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#define flush_cache_vmap(start, end) do {} while(0)
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#define flush_cache_vunmap(start, end) do {} while(0)
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#define flush_dcache_mmap_lock(mapping) do {} while(0)
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#define flush_dcache_mmap_unlock(mapping) do {} while(0)
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/*
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* physically-indexed cache management
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* - see arch/frv/lib/cache.S
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*/
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extern void frv_dcache_writeback(unsigned long start, unsigned long size);
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extern void frv_cache_invalidate(unsigned long start, unsigned long size);
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extern void frv_icache_invalidate(unsigned long start, unsigned long size);
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extern void frv_cache_wback_inv(unsigned long start, unsigned long size);
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static inline void __flush_cache_all(void)
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{
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asm volatile(" dcef @(gr0,gr0),#1 \n"
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" icei @(gr0,gr0),#1 \n"
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" membar \n"
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: : : "memory"
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);
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}
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/* dcache/icache coherency... */
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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#ifdef CONFIG_MMU
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extern void flush_dcache_page(struct page *page);
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#else
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static inline void flush_dcache_page(struct page *page)
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{
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unsigned long addr = page_to_phys(page);
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frv_dcache_writeback(addr, addr + PAGE_SIZE);
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}
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#endif
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static inline void flush_page_to_ram(struct page *page)
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{
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flush_dcache_page(page);
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}
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static inline void flush_icache(void)
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{
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__flush_cache_all();
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}
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static inline void flush_icache_range(unsigned long start, unsigned long end)
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{
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frv_cache_wback_inv(start, end);
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}
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#ifdef CONFIG_MMU
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extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
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unsigned long start, unsigned long len);
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#else
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static inline void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
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unsigned long start, unsigned long len)
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{
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frv_cache_wback_inv(start, start + len);
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}
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#endif
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static inline void flush_icache_page(struct vm_area_struct *vma, struct page *page)
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{
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flush_icache_user_range(vma, page, page_to_phys(page), PAGE_SIZE);
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}
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/*
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* permit ptrace to access another process's address space through the icache
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* and the dcache
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*/
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy((dst), (src), (len)); \
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flush_icache_user_range((vma), (page), (vaddr), (len)); \
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} while(0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy((dst), (src), (len))
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#endif /* _ASM_CACHEFLUSH_H */
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