mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 03:57:07 +07:00
0ed61fc9da
Switch the sh7372 CPU support to use CMT2 instead of CMT1 for system timer. CMT1 is located in the A3SP power domain while CMT2 is located in the always-on power domain C5. This improves our PM situation - with CMT2 as timer we can power down A3SP and still access the timer. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
704 lines
22 KiB
C
704 lines
22 KiB
C
/*
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* SH7372 clock framework support
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*
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* Copyright (C) 2010 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/common.h>
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/* SH7372 registers */
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#define FRQCRA 0xe6150000
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#define FRQCRB 0xe6150004
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#define FRQCRC 0xe61500e0
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#define FRQCRD 0xe61500e4
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#define VCLKCR1 0xe6150008
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#define VCLKCR2 0xe615000c
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#define VCLKCR3 0xe615001c
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#define FMSICKCR 0xe6150010
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#define FMSOCKCR 0xe6150014
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#define FSIACKCR 0xe6150018
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#define FSIBCKCR 0xe6150090
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#define SUBCKCR 0xe6150080
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#define SPUCKCR 0xe6150084
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#define VOUCKCR 0xe6150088
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#define HDMICKCR 0xe6150094
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#define DSITCKCR 0xe6150060
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#define DSI0PCKCR 0xe6150064
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#define DSI1PCKCR 0xe6150098
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#define PLLC01CR 0xe6150028
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#define PLLC2CR 0xe615002c
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#define RMSTPCR0 0xe6150110
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#define RMSTPCR1 0xe6150114
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#define RMSTPCR2 0xe6150118
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#define RMSTPCR3 0xe615011c
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#define RMSTPCR4 0xe6150120
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#define SMSTPCR0 0xe6150130
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#define SMSTPCR1 0xe6150134
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#define SMSTPCR2 0xe6150138
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR4 0xe6150140
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#define FSIDIVA 0xFE1F8000
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#define FSIDIVB 0xFE1F8008
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/* Platforms must set frequency on their DV_CLKI pin */
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struct clk sh7372_dv_clki_clk = {
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};
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/* Fixed 32 KHz root clock from EXTALR pin */
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static struct clk r_clk = {
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.rate = 32768,
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};
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/*
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* 26MHz default rate for the EXTAL1 root input clock.
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* If needed, reset this with clk_set_rate() from the platform code.
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*/
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struct clk sh7372_extal1_clk = {
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.rate = 26000000,
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};
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/*
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* 48MHz default rate for the EXTAL2 root input clock.
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* If needed, reset this with clk_set_rate() from the platform code.
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*/
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struct clk sh7372_extal2_clk = {
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.rate = 48000000,
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};
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/* A fixed divide-by-2 block */
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static unsigned long div2_recalc(struct clk *clk)
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{
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return clk->parent->rate / 2;
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}
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static struct clk_ops div2_clk_ops = {
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.recalc = div2_recalc,
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};
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/* Divide dv_clki by two */
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struct clk sh7372_dv_clki_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &sh7372_dv_clki_clk,
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};
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/* Divide extal1 by two */
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static struct clk extal1_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &sh7372_extal1_clk,
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};
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/* Divide extal2 by two */
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static struct clk extal2_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &sh7372_extal2_clk,
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};
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/* Divide extal2 by four */
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static struct clk extal2_div4_clk = {
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.ops = &div2_clk_ops,
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.parent = &extal2_div2_clk,
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};
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/* PLLC0 and PLLC1 */
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static unsigned long pllc01_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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if (__raw_readl(PLLC01CR) & (1 << 14))
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mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
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return clk->parent->rate * mult;
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}
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static struct clk_ops pllc01_clk_ops = {
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.recalc = pllc01_recalc,
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};
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static struct clk pllc0_clk = {
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.ops = &pllc01_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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.parent = &extal1_div2_clk,
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.enable_reg = (void __iomem *)FRQCRC,
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};
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static struct clk pllc1_clk = {
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.ops = &pllc01_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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.parent = &extal1_div2_clk,
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.enable_reg = (void __iomem *)FRQCRA,
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};
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/* Divide PLLC1 by two */
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static struct clk pllc1_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &pllc1_clk,
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};
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/* PLLC2 */
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/* Indices are important - they are the actual src selecting values */
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static struct clk *pllc2_parent[] = {
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[0] = &extal1_div2_clk,
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[1] = &extal2_div2_clk,
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[2] = &sh7372_dv_clki_div2_clk,
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};
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/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
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static struct cpufreq_frequency_table pllc2_freq_table[29];
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static void pllc2_table_rebuild(struct clk *clk)
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{
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int i;
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/* Initialise PLLC2 frequency table */
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for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
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pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
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pllc2_freq_table[i].index = i;
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}
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/* This is a special entry - switching PLL off makes it a repeater */
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pllc2_freq_table[i].frequency = clk->parent->rate;
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pllc2_freq_table[i].index = i;
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pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
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pllc2_freq_table[i].index = i;
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}
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static unsigned long pllc2_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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pllc2_table_rebuild(clk);
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/*
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* If the PLL is off, mult == 1, clk->rate will be updated in
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* pllc2_enable().
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*/
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if (__raw_readl(PLLC2CR) & (1 << 31))
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mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
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return clk->parent->rate * mult;
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}
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static long pllc2_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk_rate_table_round(clk, clk->freq_table, rate);
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}
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static int pllc2_enable(struct clk *clk)
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{
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int i;
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__raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR);
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for (i = 0; i < 100; i++)
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if (__raw_readl(PLLC2CR) & 0x80000000) {
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clk->rate = pllc2_recalc(clk);
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return 0;
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}
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pr_err("%s(): timeout!\n", __func__);
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return -ETIMEDOUT;
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}
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static void pllc2_disable(struct clk *clk)
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{
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__raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
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}
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static int pllc2_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long value;
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int idx;
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idx = clk_rate_table_find(clk, clk->freq_table, rate);
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if (idx < 0)
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return idx;
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if (rate == clk->parent->rate)
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return -EINVAL;
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value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
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__raw_writel(value | ((idx + 19) << 24), PLLC2CR);
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clk->rate = clk->freq_table[idx].frequency;
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return 0;
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}
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static int pllc2_set_parent(struct clk *clk, struct clk *parent)
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{
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u32 value;
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int ret, i;
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if (!clk->parent_table || !clk->parent_num)
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return -EINVAL;
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/* Search the parent */
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for (i = 0; i < clk->parent_num; i++)
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if (clk->parent_table[i] == parent)
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break;
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if (i == clk->parent_num)
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return -ENODEV;
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ret = clk_reparent(clk, parent);
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if (ret < 0)
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return ret;
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value = __raw_readl(PLLC2CR) & ~(3 << 6);
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__raw_writel(value | (i << 6), PLLC2CR);
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/* Rebiuld the frequency table */
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pllc2_table_rebuild(clk);
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return 0;
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}
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static struct clk_ops pllc2_clk_ops = {
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.recalc = pllc2_recalc,
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.round_rate = pllc2_round_rate,
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.set_rate = pllc2_set_rate,
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.enable = pllc2_enable,
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.disable = pllc2_disable,
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.set_parent = pllc2_set_parent,
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};
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struct clk sh7372_pllc2_clk = {
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.ops = &pllc2_clk_ops,
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.parent = &extal1_div2_clk,
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.freq_table = pllc2_freq_table,
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.nr_freqs = ARRAY_SIZE(pllc2_freq_table) - 1,
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.parent_table = pllc2_parent,
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.parent_num = ARRAY_SIZE(pllc2_parent),
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};
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/* External input clock (pin name: FSIACK/FSIBCK ) */
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struct clk sh7372_fsiack_clk = {
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};
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struct clk sh7372_fsibck_clk = {
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};
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static struct clk *main_clks[] = {
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&sh7372_dv_clki_clk,
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&r_clk,
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&sh7372_extal1_clk,
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&sh7372_extal2_clk,
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&sh7372_dv_clki_div2_clk,
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&extal1_div2_clk,
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&extal2_div2_clk,
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&extal2_div4_clk,
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&pllc0_clk,
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&pllc1_clk,
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&pllc1_div2_clk,
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&sh7372_pllc2_clk,
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&sh7372_fsiack_clk,
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&sh7372_fsibck_clk,
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};
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static void div4_kick(struct clk *clk)
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{
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unsigned long value;
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/* set KICK bit in FRQCRB to update hardware setting */
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value = __raw_readl(FRQCRB);
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value |= (1 << 31);
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__raw_writel(value, FRQCRB);
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}
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static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
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24, 32, 36, 48, 0, 72, 96, 0 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = divisors,
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.nr_divisors = ARRAY_SIZE(divisors),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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.kick = div4_kick,
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};
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enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
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DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP,
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DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
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DIV4_DDRP, DIV4_NR };
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
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static struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
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[DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
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[DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
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[DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
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[DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
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[DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
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[DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
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[DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
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[DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
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[DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
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[DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
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};
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enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
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DIV6_SUB, DIV6_SPU,
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DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
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DIV6_NR };
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static struct clk div6_clks[DIV6_NR] = {
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[DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
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[DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
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[DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
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[DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
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[DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
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[DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
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[DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
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[DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
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[DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
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[DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
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[DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
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};
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enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR };
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/* Indices are important - they are the actual src selecting values */
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static struct clk *hdmi_parent[] = {
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[0] = &pllc1_div2_clk,
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[1] = &sh7372_pllc2_clk,
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[2] = &sh7372_dv_clki_clk,
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[3] = NULL, /* pllc2_div4 not implemented yet */
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};
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static struct clk *fsiackcr_parent[] = {
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[0] = &pllc1_div2_clk,
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[1] = &sh7372_pllc2_clk,
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[2] = &sh7372_fsiack_clk, /* external input for FSI A */
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[3] = NULL, /* setting prohibited */
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};
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static struct clk *fsibckcr_parent[] = {
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[0] = &pllc1_div2_clk,
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[1] = &sh7372_pllc2_clk,
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[2] = &sh7372_fsibck_clk, /* external input for FSI B */
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[3] = NULL, /* setting prohibited */
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};
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static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
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[DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
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hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
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[DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0,
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fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
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[DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0,
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fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
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};
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/* FSI DIV */
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static unsigned long fsidiv_recalc(struct clk *clk)
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{
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unsigned long value;
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value = __raw_readl(clk->mapping->base);
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value >>= 16;
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if (value < 2)
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return 0;
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return clk->parent->rate / value;
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}
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static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk_rate_div_range_round(clk, 2, 0xffff, rate);
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}
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static void fsidiv_disable(struct clk *clk)
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{
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__raw_writel(0, clk->mapping->base);
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}
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static int fsidiv_enable(struct clk *clk)
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{
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unsigned long value;
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value = __raw_readl(clk->mapping->base) >> 16;
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if (value < 2)
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return -EIO;
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__raw_writel((value << 16) | 0x3, clk->mapping->base);
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return 0;
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}
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static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
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{
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int idx;
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idx = (clk->parent->rate / rate) & 0xffff;
|
|
if (idx < 2)
|
|
return -EINVAL;
|
|
|
|
__raw_writel(idx << 16, clk->mapping->base);
|
|
return 0;
|
|
}
|
|
|
|
static struct clk_ops fsidiv_clk_ops = {
|
|
.recalc = fsidiv_recalc,
|
|
.round_rate = fsidiv_round_rate,
|
|
.set_rate = fsidiv_set_rate,
|
|
.enable = fsidiv_enable,
|
|
.disable = fsidiv_disable,
|
|
};
|
|
|
|
static struct clk_mapping sh7372_fsidiva_clk_mapping = {
|
|
.phys = FSIDIVA,
|
|
.len = 8,
|
|
};
|
|
|
|
struct clk sh7372_fsidiva_clk = {
|
|
.ops = &fsidiv_clk_ops,
|
|
.parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
|
|
.mapping = &sh7372_fsidiva_clk_mapping,
|
|
};
|
|
|
|
static struct clk_mapping sh7372_fsidivb_clk_mapping = {
|
|
.phys = FSIDIVB,
|
|
.len = 8,
|
|
};
|
|
|
|
struct clk sh7372_fsidivb_clk = {
|
|
.ops = &fsidiv_clk_ops,
|
|
.parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
|
|
.mapping = &sh7372_fsidivb_clk_mapping,
|
|
};
|
|
|
|
static struct clk *late_main_clks[] = {
|
|
&sh7372_fsidiva_clk,
|
|
&sh7372_fsidivb_clk,
|
|
};
|
|
|
|
enum { MSTP001,
|
|
MSTP131, MSTP130,
|
|
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
|
|
MSTP118, MSTP117, MSTP116, MSTP113,
|
|
MSTP106, MSTP101, MSTP100,
|
|
MSTP223,
|
|
MSTP218, MSTP217, MSTP216,
|
|
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
|
MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
|
|
MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403, MSTP400,
|
|
MSTP_NR };
|
|
|
|
#define MSTP(_parent, _reg, _bit, _flags) \
|
|
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
|
|
|
|
static struct clk mstp_clks[MSTP_NR] = {
|
|
[MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
|
|
[MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
|
|
[MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
|
|
[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
|
|
[MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
|
|
[MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
|
|
[MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
|
|
[MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
|
|
[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
|
|
[MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
|
|
[MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
|
|
[MSTP113] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 13, 0), /* MERAM */
|
|
[MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
|
|
[MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
|
|
[MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
|
|
[MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
|
|
[MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
|
|
[MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
|
|
[MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
|
|
[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
|
|
[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
|
|
[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
|
|
[MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
|
|
[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
|
|
[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
|
|
[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
|
|
[MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
|
|
[MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
|
|
[MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
|
|
[MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
|
|
[MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
|
|
[MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
|
|
[MSTP423] = MSTP(&div4_clks[DIV4_B], SMSTPCR4, 23, 0), /* DSITX1 */
|
|
[MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
|
|
[MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
|
|
[MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
|
|
[MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
|
|
[MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
|
|
[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
|
|
[MSTP400] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* CMT2 */
|
|
};
|
|
|
|
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
|
|
#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
|
|
#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
|
|
|
|
static struct clk_lookup lookups[] = {
|
|
/* main clocks */
|
|
CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk),
|
|
CLKDEV_CON_ID("r_clk", &r_clk),
|
|
CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
|
|
CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
|
|
CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
|
|
CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
|
|
CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
|
|
CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
|
|
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
|
|
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
|
|
CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
|
|
|
|
/* DIV4 clocks */
|
|
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
|
|
CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
|
|
CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
|
|
CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
|
|
CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
|
|
CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
|
|
CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
|
|
CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
|
|
CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
|
|
CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
|
|
CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
|
|
CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
|
|
CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
|
|
CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
|
|
CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),
|
|
|
|
/* DIV6 clocks */
|
|
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
|
|
CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
|
|
CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
|
|
CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
|
|
CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
|
|
CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
|
|
CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
|
|
CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
|
|
CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
|
|
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
|
|
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
|
|
CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
|
|
CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
|
|
|
|
/* MSTP32 clocks */
|
|
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
|
|
CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
|
|
CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
|
|
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
|
|
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
|
|
CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
|
|
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
|
|
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
|
|
CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[MSTP113]), /* MERAM */
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
|
|
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
|
|
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* DMAC1 */
|
|
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */
|
|
CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */
|
|
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
|
|
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
|
|
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
|
|
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
|
|
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
|
|
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
|
|
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
|
|
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
|
|
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
|
|
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
|
|
CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
|
|
CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */
|
|
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
|
|
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
|
|
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
|
|
CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */
|
|
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
|
|
CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
|
|
CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
|
|
CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
|
|
CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
|
|
CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
|
|
CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
|
|
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
|
|
CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */
|
|
|
|
CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
|
|
CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
|
|
CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
|
|
};
|
|
|
|
void __init sh7372_clock_init(void)
|
|
{
|
|
int k, ret = 0;
|
|
|
|
/* make sure MSTP bits on the RT/SH4AL-DSP side are off */
|
|
__raw_writel(0xe4ef8087, RMSTPCR0);
|
|
__raw_writel(0xffffffff, RMSTPCR1);
|
|
__raw_writel(0x37c7f7ff, RMSTPCR2);
|
|
__raw_writel(0xffffffff, RMSTPCR3);
|
|
__raw_writel(0xffe0fffd, RMSTPCR4);
|
|
|
|
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
|
ret = clk_register(main_clks[k]);
|
|
|
|
if (!ret)
|
|
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
|
|
|
if (!ret)
|
|
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
|
|
|
|
if (!ret)
|
|
ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
|
|
|
|
if (!ret)
|
|
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
|
|
|
|
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
|
|
ret = clk_register(late_main_clks[k]);
|
|
|
|
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
|
|
|
if (!ret)
|
|
clk_init();
|
|
else
|
|
panic("failed to setup sh7372 clocks\n");
|
|
|
|
}
|