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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6f95e60acf
Patch to add PCI support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
206 lines
7.4 KiB
C
206 lines
7.4 KiB
C
/*
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* Copyright (c) 2000-2006 PMC-Sierra INC.
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*
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* This program is free software; you can redistribute it
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* and/or modify it under the terms of the GNU General
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* Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be
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* useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this program; if not, write to the Free
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* Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
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* 02139, USA.
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*
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* PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
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* SOFTWARE.
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*/
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#ifndef _MSP_PCI_H_
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#define _MSP_PCI_H_
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#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220))
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/*
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* It is convenient to program the OATRAN register so that
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* Athena virtual address space and PCI address space are
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* the same. This is not a requirement, just a convenience.
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*
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* The only hard restrictions on the value of OATRAN is that
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* OATRAN must not be programmed to allow translated memory
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* addresses to fall within the lowest 512MB of
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* PCI address space. This region is hardcoded
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* for use as Athena PCI Host Controller target
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* access memory space to the Athena's SDRAM.
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*
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* Note that OATRAN applies only to memory accesses, not
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* to I/O accesses.
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*
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* To program OATRAN to make Athena virtual address space
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* and PCI address space have the same values, OATRAN
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* is to be programmed to 0xB8000000. The top seven
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* bits of the value mimic the seven bits clipped off
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* by the PCI Host controller.
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*
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* With OATRAN at the said value, when the CPU does
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* an access to its virtual address at, say 0xB900_5000,
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* the address appearing on the PCI bus will be
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* 0xB900_5000.
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* - Michael Penner
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*/
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#define MSP_PCI_OATRAN 0xB8000000UL
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#define MSP_PCI_SPACE_BASE (MSP_PCI_OATRAN + 0x1002000UL)
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#define MSP_PCI_SPACE_SIZE (0x3000000UL - 0x2000)
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#define MSP_PCI_SPACE_END \
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(MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1)
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#define MSP_PCI_IOSPACE_BASE (MSP_PCI_OATRAN + 0x1001000UL)
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#define MSP_PCI_IOSPACE_SIZE 0x1000
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#define MSP_PCI_IOSPACE_END \
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(MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1)
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/* IRQ for PCI status interrupts */
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#define PCI_STAT_IRQ 20
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#define QFLUSH_REG_1 0xB7F40000
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typedef volatile unsigned int pcireg;
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typedef void * volatile ppcireg;
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struct pci_block_copy
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{
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pcireg unused1; /* +0x00 */
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pcireg unused2; /* +0x04 */
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ppcireg unused3; /* +0x08 */
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ppcireg unused4; /* +0x0C */
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pcireg unused5; /* +0x10 */
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pcireg unused6; /* +0x14 */
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pcireg unused7; /* +0x18 */
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ppcireg unused8; /* +0x1C */
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ppcireg unused9; /* +0x20 */
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pcireg unusedA; /* +0x24 */
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ppcireg unusedB; /* +0x28 */
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ppcireg unusedC; /* +0x2C */
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};
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enum
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{
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config_device_vendor, /* 0 */
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config_status_command, /* 1 */
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config_class_revision, /* 2 */
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config_BIST_header_latency_cache, /* 3 */
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config_BAR0, /* 4 */
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config_BAR1, /* 5 */
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config_BAR2, /* 6 */
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config_not_used7, /* 7 */
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config_not_used8, /* 8 */
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config_not_used9, /* 9 */
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config_CIS, /* 10 */
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config_subsystem, /* 11 */
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config_not_used12, /* 12 */
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config_capabilities, /* 13 */
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config_not_used14, /* 14 */
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config_lat_grant_irq, /* 15 */
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config_message_control,/* 16 */
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config_message_addr, /* 17 */
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config_message_data, /* 18 */
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config_VPD_addr, /* 19 */
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config_VPD_data, /* 20 */
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config_maxregs /* 21 - number of registers */
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};
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struct msp_pci_regs
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{
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pcireg hop_unused_00; /* +0x00 */
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pcireg hop_unused_04; /* +0x04 */
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pcireg hop_unused_08; /* +0x08 */
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pcireg hop_unused_0C; /* +0x0C */
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pcireg hop_unused_10; /* +0x10 */
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pcireg hop_unused_14; /* +0x14 */
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pcireg hop_unused_18; /* +0x18 */
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pcireg hop_unused_1C; /* +0x1C */
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pcireg hop_unused_20; /* +0x20 */
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pcireg hop_unused_24; /* +0x24 */
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pcireg hop_unused_28; /* +0x28 */
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pcireg hop_unused_2C; /* +0x2C */
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pcireg hop_unused_30; /* +0x30 */
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pcireg hop_unused_34; /* +0x34 */
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pcireg if_control; /* +0x38 */
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pcireg oatran; /* +0x3C */
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pcireg reset_ctl; /* +0x40 */
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pcireg config_addr; /* +0x44 */
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pcireg hop_unused_48; /* +0x48 */
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pcireg msg_signaled_int_status; /* +0x4C */
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pcireg msg_signaled_int_mask; /* +0x50 */
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pcireg if_status; /* +0x54 */
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pcireg if_mask; /* +0x58 */
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pcireg hop_unused_5C; /* +0x5C */
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pcireg hop_unused_60; /* +0x60 */
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pcireg hop_unused_64; /* +0x64 */
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pcireg hop_unused_68; /* +0x68 */
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pcireg hop_unused_6C; /* +0x6C */
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pcireg hop_unused_70; /* +0x70 */
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struct pci_block_copy pci_bc[2] __attribute__((aligned(64)));
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pcireg error_hdr1; /* +0xE0 */
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pcireg error_hdr2; /* +0xE4 */
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pcireg config[config_maxregs] __attribute__((aligned(256)));
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};
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#define BPCI_CFGADDR_BUSNUM_SHF 16
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#define BPCI_CFGADDR_FUNCTNUM_SHF 8
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#define BPCI_CFGADDR_REGNUM_SHF 2
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#define BPCI_CFGADDR_ENABLE (1<<31)
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#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */
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#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */
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#define BPCI_IFCONTROL_CTO_SHF 12 /* Shift count for CTO bits */
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#define BPCI_IFCONTROL_SE (1<<5) /* Enable exceptions on errors */
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#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */
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#define BPCI_IFCONTROL_CAP (1<<3) /* Enable capabilities */
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#define BPCI_IFCONTROL_MMC_SHF 0 /* Shift count for MMC bits */
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#define BPCI_IFSTATUS_MGT (1<<8) /* Master Grant timeout */
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#define BPCI_IFSTATUS_MTT (1<<9) /* Master TRDY timeout */
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#define BPCI_IFSTATUS_MRT (1<<10) /* Master retry timeout */
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#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */
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#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */
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#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */
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#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */
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#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */
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#define BPCI_IFSTATUS_RTO (1<<18) /* Retry time out */
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#define BPCI_IFSTATUS_SER (1<<19) /* System error */
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#define BPCI_IFSTATUS_PER (1<<20) /* Parity error */
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#define BPCI_IFSTATUS_LCA (1<<21) /* Local CPU abort */
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#define BPCI_IFSTATUS_MEM (1<<22) /* Memory prot. violation */
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#define BPCI_IFSTATUS_ARB (1<<23) /* Arbiter timed out */
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#define BPCI_IFSTATUS_STA (1<<27) /* Signaled target abort */
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#define BPCI_IFSTATUS_TA (1<<28) /* Target abort */
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#define BPCI_IFSTATUS_MA (1<<29) /* Master abort */
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#define BPCI_IFSTATUS_PEI (1<<30) /* Parity error as initiator */
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#define BPCI_IFSTATUS_PET (1<<31) /* Parity error as target */
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#define BPCI_RESETCTL_PR (1<<0) /* True if reset asserted */
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#define BPCI_RESETCTL_RT (1<<4) /* Release time */
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#define BPCI_RESETCTL_CT (1<<8) /* Config time */
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#define BPCI_RESETCTL_PE (1<<12) /* PCI enabled */
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#define BPCI_RESETCTL_HM (1<<13) /* PCI host mode */
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#define BPCI_RESETCTL_RI (1<<14) /* PCI reset in */
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extern struct msp_pci_regs msp_pci_regs
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__attribute__((section(".register")));
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extern unsigned long msp_pci_config_space
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__attribute__((section(".register")));
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#endif /* !_MSP_PCI_H_ */
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