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0f67e90e1c
The LL / SC loops in __futex_atomic_op() have the usual fixups necessary
for memory acccesses to userspace from kernel space installed:
__asm__ __volatile__(
" .set push \n"
" .set noat \n"
" .set mips3 \n"
"1: ll %1, %4 # __futex_atomic_op \n"
" .set mips0 \n"
" " insn " \n"
" .set mips3 \n"
"2: sc $1, %2 \n"
" beqz $1, 1b \n"
__WEAK_LLSC_MB
"3: \n"
" .set pop \n"
" .set mips0 \n"
" .section .fixup,\"ax\" \n"
"4: li %0, %6 \n"
" j 2b \n" <-----
" .previous \n"
" .section __ex_table,\"a\" \n"
" "__UA_ADDR "\t1b, 4b \n"
" "__UA_ADDR "\t2b, 4b \n"
" .previous \n"
: "=r" (ret), "=&r" (oldval), "=R" (*uaddr)
: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)
: "memory");
The branch at the end of the fixup code, it goes back to the SC
instruction, no matter if the fault was first taken by the LL or SC
instruction resulting in an endless loop which will only terminate if
the address become valid again due to another thread setting up an
accessible mapping and the CPU happens to execute the SC instruction
successfully which due to the preceeding ERET instruction of the fault
handler would only happen if UNPREDICTABLE instruction behaviour of the
SC instruction without a preceeding LL happens to favor that outcome.
But normally processes are nice, pass valid arguments and we were just
getting away with this.
Thanks to Kaz Kylheku <kaz@zeugmasystems.com> for providing the original
report and a test case.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
204 lines
5.1 KiB
C
204 lines
5.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 2006 Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef _ASM_FUTEX_H
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#define _ASM_FUTEX_H
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#ifdef __KERNEL__
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#include <linux/futex.h>
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#include <asm/barrier.h>
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#include <asm/errno.h>
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#include <asm/uaccess.h>
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#include <asm/war.h>
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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{ \
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if (cpu_has_llsc && R10000_LLSC_WAR) { \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noat \n" \
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" .set mips3 \n" \
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"1: ll %1, %4 # __futex_atomic_op \n" \
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" .set mips0 \n" \
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" " insn " \n" \
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" .set mips3 \n" \
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"2: sc $1, %2 \n" \
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" beqzl $1, 1b \n" \
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__WEAK_LLSC_MB \
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"3: \n" \
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" .set pop \n" \
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" .set mips0 \n" \
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" .section .fixup,\"ax\" \n" \
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"4: li %0, %6 \n" \
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" j 3b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" "__UA_ADDR "\t1b, 4b \n" \
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" "__UA_ADDR "\t2b, 4b \n" \
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" .previous \n" \
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: "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
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: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
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: "memory"); \
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} else if (cpu_has_llsc) { \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noat \n" \
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" .set mips3 \n" \
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"1: ll %1, %4 # __futex_atomic_op \n" \
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" .set mips0 \n" \
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" " insn " \n" \
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" .set mips3 \n" \
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"2: sc $1, %2 \n" \
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" beqz $1, 1b \n" \
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__WEAK_LLSC_MB \
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"3: \n" \
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" .set pop \n" \
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" .set mips0 \n" \
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" .section .fixup,\"ax\" \n" \
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"4: li %0, %6 \n" \
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" j 3b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" "__UA_ADDR "\t1b, 4b \n" \
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" "__UA_ADDR "\t2b, 4b \n" \
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" .previous \n" \
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: "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
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: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
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: "memory"); \
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} else \
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ret = -ENOSYS; \
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}
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static inline int
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futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
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{
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int op = (encoded_op >> 28) & 7;
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int cmp = (encoded_op >> 24) & 15;
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int oparg = (encoded_op << 8) >> 20;
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int cmparg = (encoded_op << 20) >> 20;
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int oldval = 0, ret;
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if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
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oparg = 1 << oparg;
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if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
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return -EFAULT;
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ADD:
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__futex_atomic_op("addu $1, %1, %z5",
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ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op("or $1, %1, %z5",
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ret, oldval, uaddr, oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op("and $1, %1, %z5",
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ret, oldval, uaddr, ~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op("xor $1, %1, %z5",
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ret, oldval, uaddr, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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pagefault_enable();
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if (!ret) {
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switch (cmp) {
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case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
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case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
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case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
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case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
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case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
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case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
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default: ret = -ENOSYS;
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}
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}
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return ret;
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}
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static inline int
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futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
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{
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int retval;
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
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return -EFAULT;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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__asm__ __volatile__(
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"# futex_atomic_cmpxchg_inatomic \n"
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" .set push \n"
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" .set noat \n"
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" .set mips3 \n"
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"1: ll %0, %2 \n"
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" bne %0, %z3, 3f \n"
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" .set mips0 \n"
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" move $1, %z4 \n"
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" .set mips3 \n"
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"2: sc $1, %1 \n"
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" beqzl $1, 1b \n"
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__WEAK_LLSC_MB
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"3: \n"
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" .set pop \n"
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" .section .fixup,\"ax\" \n"
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"4: li %0, %5 \n"
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" j 3b \n"
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" .previous \n"
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" .section __ex_table,\"a\" \n"
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" "__UA_ADDR "\t1b, 4b \n"
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" "__UA_ADDR "\t2b, 4b \n"
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" .previous \n"
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: "=&r" (retval), "=R" (*uaddr)
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: "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
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: "memory");
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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"# futex_atomic_cmpxchg_inatomic \n"
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" .set push \n"
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" .set noat \n"
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" .set mips3 \n"
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"1: ll %0, %2 \n"
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" bne %0, %z3, 3f \n"
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" .set mips0 \n"
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" move $1, %z4 \n"
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" .set mips3 \n"
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"2: sc $1, %1 \n"
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" beqz $1, 1b \n"
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__WEAK_LLSC_MB
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"3: \n"
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" .set pop \n"
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" .section .fixup,\"ax\" \n"
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"4: li %0, %5 \n"
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" j 3b \n"
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" .previous \n"
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" .section __ex_table,\"a\" \n"
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" "__UA_ADDR "\t1b, 4b \n"
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" "__UA_ADDR "\t2b, 4b \n"
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" .previous \n"
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: "=&r" (retval), "=R" (*uaddr)
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: "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
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: "memory");
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} else
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return -ENOSYS;
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return retval;
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}
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#endif
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#endif /* _ASM_FUTEX_H */
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