mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 07:06:59 +07:00
07acfc2a93
Pull KVM changes from Avi Kivity: "Changes include additional instruction emulation, page-crossing MMIO, faster dirty logging, preventing the watchdog from killing a stopped guest, module autoload, a new MSI ABI, and some minor optimizations and fixes. Outside x86 we have a small s390 and a very large ppc update. Regarding the new (for kvm) rebaseless workflow, some of the patches that were merged before we switch trees had to be rebased, while others are true pulls. In either case the signoffs should be correct now." Fix up trivial conflicts in Documentation/feature-removal-schedule.txt arch/powerpc/kvm/book3s_segment.S and arch/x86/include/asm/kvm_para.h. I suspect the kvm_para.h resolution ends up doing the "do I have cpuid" check effectively twice (it was done differently in two different commits), but better safe than sorry ;) * 'next' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (125 commits) KVM: make asm-generic/kvm_para.h have an ifdef __KERNEL__ block KVM: s390: onereg for timer related registers KVM: s390: epoch difference and TOD programmable field KVM: s390: KVM_GET/SET_ONEREG for s390 KVM: s390: add capability indicating COW support KVM: Fix mmu_reload() clash with nested vmx event injection KVM: MMU: Don't use RCU for lockless shadow walking KVM: VMX: Optimize %ds, %es reload KVM: VMX: Fix %ds/%es clobber KVM: x86 emulator: convert bsf/bsr instructions to emulate_2op_SrcV_nobyte() KVM: VMX: unlike vmcs on fail path KVM: PPC: Emulator: clean up SPR reads and writes KVM: PPC: Emulator: clean up instruction parsing kvm/powerpc: Add new ioctl to retreive server MMU infos kvm/book3s: Make kernel emulated H_PUT_TCE available for "PR" KVM KVM: PPC: bookehv: Fix r8/r13 storing in level exception handler KVM: PPC: Book3S: Enable IRQs during exit handling KVM: PPC: Fix PR KVM on POWER7 bare metal KVM: PPC: Fix stbux emulation KVM: PPC: bookehv: Use lwz/stw instead of PPC_LL/PPC_STL for 32-bit fields ...
1135 lines
29 KiB
ArmAsm
1135 lines
29 KiB
ArmAsm
/*
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* Kernel execution entry point code.
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*
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* Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
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* Initial PowerPC version.
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* Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Rewritten for PReP
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* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
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* Low-level exception handers, MMU support, and rewrite.
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* Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
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* PowerPC 8xx modifications.
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* Copyright (c) 1998-1999 TiVo, Inc.
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* PowerPC 403GCX modifications.
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* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
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* PowerPC 403GCX/405GP modifications.
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* Copyright 2000 MontaVista Software Inc.
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* PPC405 modifications
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* PowerPC 403GCX/405GP modifications.
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* Author: MontaVista Software, Inc.
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* frank_rowand@mvista.com or source@mvista.com
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* debbie_chu@mvista.com
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* Copyright 2002-2004 MontaVista Software, Inc.
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* PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2004 Freescale Semiconductor, Inc
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* PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/threads.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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#include <asm/ptrace.h>
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#include "head_booke.h"
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/* As with the other PowerPC ports, it is expected that when code
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* execution begins here, the following registers contain valid, yet
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* optional, information:
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*
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* r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
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* r4 - Starting address of the init RAM disk
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* r5 - Ending address of the init RAM disk
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* r6 - Start of kernel command line string (e.g. "mem=128")
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* r7 - End of kernel command line string
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*
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*/
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__HEAD
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_ENTRY(_stext);
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_ENTRY(_start);
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/*
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* Reserve a word at a fixed location to store the address
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* of abatron_pteptrs
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*/
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nop
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/* Translate device tree address to physical, save in r30/r31 */
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mfmsr r16
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mfspr r17,SPRN_PID
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rlwinm r17,r17,16,0x3fff0000 /* turn PID into MAS6[SPID] */
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rlwimi r17,r16,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
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mtspr SPRN_MAS6,r17
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tlbsx 0,r3 /* must succeed */
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mfspr r16,SPRN_MAS1
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mfspr r20,SPRN_MAS3
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rlwinm r17,r16,25,0x1f /* r17 = log2(page size) */
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li r18,1024
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slw r18,r18,r17 /* r18 = page size */
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addi r18,r18,-1
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and r19,r3,r18 /* r19 = page offset */
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andc r31,r20,r18 /* r31 = page base */
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or r31,r31,r19 /* r31 = devtree phys addr */
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mfspr r30,SPRN_MAS7
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li r25,0 /* phys kernel start (low) */
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li r24,0 /* CPU number */
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li r23,0 /* phys kernel start (high) */
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/* We try to not make any assumptions about how the boot loader
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* setup or used the TLBs. We invalidate all mappings from the
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* boot loader and load a single entry in TLB1[0] to map the
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* first 64M of kernel memory. Any boot info passed from the
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* bootloader needs to live in this first 64M.
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*
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* Requirement on bootloader:
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* - The page we're executing in needs to reside in TLB1 and
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* have IPROT=1. If not an invalidate broadcast could
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* evict the entry we're currently executing in.
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*
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* r3 = Index of TLB1 were executing in
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* r4 = Current MSR[IS]
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* r5 = Index of TLB1 temp mapping
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*
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* Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
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* if needed
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*/
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_ENTRY(__early_start)
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#define ENTRY_MAPPING_BOOT_SETUP
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#include "fsl_booke_entry_mapping.S"
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#undef ENTRY_MAPPING_BOOT_SETUP
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/* Establish the interrupt vector offsets */
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SET_IVOR(0, CriticalInput);
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SET_IVOR(1, MachineCheck);
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SET_IVOR(2, DataStorage);
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SET_IVOR(3, InstructionStorage);
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SET_IVOR(4, ExternalInput);
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SET_IVOR(5, Alignment);
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SET_IVOR(6, Program);
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SET_IVOR(7, FloatingPointUnavailable);
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SET_IVOR(8, SystemCall);
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SET_IVOR(9, AuxillaryProcessorUnavailable);
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SET_IVOR(10, Decrementer);
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SET_IVOR(11, FixedIntervalTimer);
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SET_IVOR(12, WatchdogTimer);
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SET_IVOR(13, DataTLBError);
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SET_IVOR(14, InstructionTLBError);
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SET_IVOR(15, DebugCrit);
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/* Establish the interrupt vector base */
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lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
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mtspr SPRN_IVPR,r4
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/* Setup the defaults for TLB entries */
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li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
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#ifdef CONFIG_E200
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oris r2,r2,MAS4_TLBSELD(1)@h
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#endif
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mtspr SPRN_MAS4, r2
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#if 0
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/* Enable DOZE */
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mfspr r2,SPRN_HID0
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oris r2,r2,HID0_DOZE@h
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mtspr SPRN_HID0, r2
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#endif
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#if !defined(CONFIG_BDI_SWITCH)
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/*
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* The Abatron BDI JTAG debugger does not tolerate others
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* mucking with the debug registers.
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*/
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lis r2,DBCR0_IDM@h
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mtspr SPRN_DBCR0,r2
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isync
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/* clear any residual debug events */
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li r2,-1
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mtspr SPRN_DBSR,r2
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#endif
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#ifdef CONFIG_SMP
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/* Check to see if we're the second processor, and jump
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* to the secondary_start code if so
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*/
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lis r24, boot_cpuid@h
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ori r24, r24, boot_cpuid@l
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lwz r24, 0(r24)
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cmpwi r24, -1
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mfspr r24,SPRN_PIR
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bne __secondary_start
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#endif
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/*
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* This is where the main kernel code starts.
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*/
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/* ptr to current */
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lis r2,init_task@h
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ori r2,r2,init_task@l
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/* ptr to current thread */
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addi r4,r2,THREAD /* init task's THREAD */
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mtspr SPRN_SPRG_THREAD,r4
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/* stack */
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lis r1,init_thread_union@h
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ori r1,r1,init_thread_union@l
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li r0,0
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stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
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rlwinm r22,r1,0,0,31-THREAD_SHIFT /* current thread_info */
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stw r24, TI_CPU(r22)
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bl early_init
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#ifdef CONFIG_DYNAMIC_MEMSTART
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lis r3,kernstart_addr@ha
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la r3,kernstart_addr@l(r3)
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#ifdef CONFIG_PHYS_64BIT
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stw r23,0(r3)
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stw r25,4(r3)
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#else
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stw r25,0(r3)
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#endif
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#endif
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/*
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* Decide what sort of machine this is and initialize the MMU.
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*/
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mr r3,r30
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mr r4,r31
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bl machine_init
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bl MMU_init
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/* Setup PTE pointers for the Abatron bdiGDB */
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lis r6, swapper_pg_dir@h
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ori r6, r6, swapper_pg_dir@l
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lis r5, abatron_pteptrs@h
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ori r5, r5, abatron_pteptrs@l
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lis r4, KERNELBASE@h
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ori r4, r4, KERNELBASE@l
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stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
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stw r6, 0(r5)
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/* Let's move on */
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lis r4,start_kernel@h
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ori r4,r4,start_kernel@l
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lis r3,MSR_KERNEL@h
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ori r3,r3,MSR_KERNEL@l
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mtspr SPRN_SRR0,r4
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mtspr SPRN_SRR1,r3
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rfi /* change context and jump to start_kernel */
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/* Macros to hide the PTE size differences
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*
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* FIND_PTE -- walks the page tables given EA & pgdir pointer
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* r10 -- EA of fault
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* r11 -- PGDIR pointer
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* r12 -- free
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* label 2: is the bailout case
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*
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* if we find the pte (fall through):
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* r11 is low pte word
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* r12 is pointer to the pte
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* r10 is the pshift from the PGD, if we're a hugepage
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*/
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#ifdef CONFIG_PTE_64BIT
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#ifdef CONFIG_HUGETLB_PAGE
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#define FIND_PTE \
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rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
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lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
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rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
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blt 1000f; /* Normal non-huge page */ \
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beq 2f; /* Bail if no table */ \
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oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
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andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
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xor r12, r10, r11; /* drop size bits from pointer */ \
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b 1001f; \
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1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
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li r10, 0; /* clear r10 */ \
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1001: lwz r11, 4(r12); /* Get pte entry */
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#else
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#define FIND_PTE \
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rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
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lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
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rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
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beq 2f; /* Bail if no table */ \
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rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
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lwz r11, 4(r12); /* Get pte entry */
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#endif /* HUGEPAGE */
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#else /* !PTE_64BIT */
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#define FIND_PTE \
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rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
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lwz r11, 0(r11); /* Get L1 entry */ \
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rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
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beq 2f; /* Bail if no table */ \
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rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
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lwz r11, 0(r12); /* Get Linux PTE */
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#endif
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/*
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* Interrupt vector entry code
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*
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* The Book E MMUs are always on so we don't need to handle
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* interrupts in real mode as with previous PPC processors. In
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* this case we handle interrupts in the kernel virtual address
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* space.
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*
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* Interrupt vectors are dynamically placed relative to the
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* interrupt prefix as determined by the address of interrupt_base.
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* The interrupt vectors offsets are programmed using the labels
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* for each interrupt vector entry.
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*
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* Interrupt vectors must be aligned on a 16 byte boundary.
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* We align on a 32 byte cache line boundary for good measure.
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*/
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interrupt_base:
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/* Critical Input Interrupt */
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CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
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/* Machine Check Interrupt */
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#ifdef CONFIG_E200
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/* no RFMCI, MCSRRs on E200 */
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CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
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machine_check_exception)
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#else
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MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
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#endif
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/* Data Storage Interrupt */
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START_EXCEPTION(DataStorage)
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NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
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mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
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stw r5,_ESR(r11)
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mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
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andis. r10,r5,(ESR_ILK|ESR_DLK)@h
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bne 1f
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EXC_XFER_LITE(0x0300, handle_page_fault)
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1:
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addi r3,r1,STACK_FRAME_OVERHEAD
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EXC_XFER_EE_LITE(0x0300, CacheLockingException)
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/* Instruction Storage Interrupt */
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INSTRUCTION_STORAGE_EXCEPTION
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/* External Input Interrupt */
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EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
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/* Alignment Interrupt */
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ALIGNMENT_EXCEPTION
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/* Program Interrupt */
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PROGRAM_EXCEPTION
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/* Floating Point Unavailable Interrupt */
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#ifdef CONFIG_PPC_FPU
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FP_UNAVAILABLE_EXCEPTION
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#else
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#ifdef CONFIG_E200
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/* E200 treats 'normal' floating point instructions as FP Unavail exception */
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EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
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program_check_exception, EXC_XFER_EE)
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#else
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EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
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unknown_exception, EXC_XFER_EE)
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#endif
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#endif
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/* System Call Interrupt */
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START_EXCEPTION(SystemCall)
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NORMAL_EXCEPTION_PROLOG(SYSCALL)
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EXC_XFER_EE_LITE(0x0c00, DoSyscall)
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/* Auxiliary Processor Unavailable Interrupt */
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EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
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unknown_exception, EXC_XFER_EE)
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/* Decrementer Interrupt */
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DECREMENTER_EXCEPTION
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/* Fixed Internal Timer Interrupt */
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/* TODO: Add FIT support */
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EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
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unknown_exception, EXC_XFER_EE)
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/* Watchdog Timer Interrupt */
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#ifdef CONFIG_BOOKE_WDT
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CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
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#else
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CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
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#endif
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/* Data TLB Error Interrupt */
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START_EXCEPTION(DataTLBError)
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mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
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mfspr r10, SPRN_SPRG_THREAD
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stw r11, THREAD_NORMSAVE(0)(r10)
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#ifdef CONFIG_KVM_BOOKE_HV
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BEGIN_FTR_SECTION
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mfspr r11, SPRN_SRR1
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END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
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#endif
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stw r12, THREAD_NORMSAVE(1)(r10)
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stw r13, THREAD_NORMSAVE(2)(r10)
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mfcr r13
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stw r13, THREAD_NORMSAVE(3)(r10)
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DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
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mfspr r10, SPRN_DEAR /* Get faulting address */
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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lis r11, PAGE_OFFSET@h
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cmplw 5, r10, r11
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blt 5, 3f
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lis r11, swapper_pg_dir@h
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ori r11, r11, swapper_pg_dir@l
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mfspr r12,SPRN_MAS1 /* Set TID to 0 */
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rlwinm r12,r12,0,16,1
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mtspr SPRN_MAS1,r12
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b 4f
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/* Get the PGD for the current thread */
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3:
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mfspr r11,SPRN_SPRG_THREAD
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lwz r11,PGDIR(r11)
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4:
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/* Mask of required permission bits. Note that while we
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* do copy ESR:ST to _PAGE_RW position as trying to write
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* to an RO page is pretty common, we don't do it with
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* _PAGE_DIRTY. We could do it, but it's a fairly rare
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* event so I'd rather take the overhead when it happens
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* rather than adding an instruction here. We should measure
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* whether the whole thing is worth it in the first place
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* as we could avoid loading SPRN_ESR completely in the first
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* place...
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*
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* TODO: Is it worth doing that mfspr & rlwimi in the first
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* place or can we save a couple of instructions here ?
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*/
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mfspr r12,SPRN_ESR
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|
#ifdef CONFIG_PTE_64BIT
|
|
li r13,_PAGE_PRESENT
|
|
oris r13,r13,_PAGE_ACCESSED@h
|
|
#else
|
|
li r13,_PAGE_PRESENT|_PAGE_ACCESSED
|
|
#endif
|
|
rlwimi r13,r12,11,29,29
|
|
|
|
FIND_PTE
|
|
andc. r13,r13,r11 /* Check permission */
|
|
|
|
#ifdef CONFIG_PTE_64BIT
|
|
#ifdef CONFIG_SMP
|
|
subf r13,r11,r12 /* create false data dep */
|
|
lwzx r13,r11,r13 /* Get upper pte bits */
|
|
#else
|
|
lwz r13,0(r12) /* Get upper pte bits */
|
|
#endif
|
|
#endif
|
|
|
|
bne 2f /* Bail if permission/valid mismach */
|
|
|
|
/* Jump to common tlb load */
|
|
b finish_tlb_load
|
|
2:
|
|
/* The bailout. Restore registers to pre-exception conditions
|
|
* and call the heavyweights to help us out.
|
|
*/
|
|
mfspr r10, SPRN_SPRG_THREAD
|
|
lwz r11, THREAD_NORMSAVE(3)(r10)
|
|
mtcr r11
|
|
lwz r13, THREAD_NORMSAVE(2)(r10)
|
|
lwz r12, THREAD_NORMSAVE(1)(r10)
|
|
lwz r11, THREAD_NORMSAVE(0)(r10)
|
|
mfspr r10, SPRN_SPRG_RSCRATCH0
|
|
b DataStorage
|
|
|
|
/* Instruction TLB Error Interrupt */
|
|
/*
|
|
* Nearly the same as above, except we get our
|
|
* information from different registers and bailout
|
|
* to a different point.
|
|
*/
|
|
START_EXCEPTION(InstructionTLBError)
|
|
mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
|
|
mfspr r10, SPRN_SPRG_THREAD
|
|
stw r11, THREAD_NORMSAVE(0)(r10)
|
|
#ifdef CONFIG_KVM_BOOKE_HV
|
|
BEGIN_FTR_SECTION
|
|
mfspr r11, SPRN_SRR1
|
|
END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
|
|
#endif
|
|
stw r12, THREAD_NORMSAVE(1)(r10)
|
|
stw r13, THREAD_NORMSAVE(2)(r10)
|
|
mfcr r13
|
|
stw r13, THREAD_NORMSAVE(3)(r10)
|
|
DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
|
|
mfspr r10, SPRN_SRR0 /* Get faulting address */
|
|
|
|
/* If we are faulting a kernel address, we have to use the
|
|
* kernel page tables.
|
|
*/
|
|
lis r11, PAGE_OFFSET@h
|
|
cmplw 5, r10, r11
|
|
blt 5, 3f
|
|
lis r11, swapper_pg_dir@h
|
|
ori r11, r11, swapper_pg_dir@l
|
|
|
|
mfspr r12,SPRN_MAS1 /* Set TID to 0 */
|
|
rlwinm r12,r12,0,16,1
|
|
mtspr SPRN_MAS1,r12
|
|
|
|
/* Make up the required permissions for kernel code */
|
|
#ifdef CONFIG_PTE_64BIT
|
|
li r13,_PAGE_PRESENT | _PAGE_BAP_SX
|
|
oris r13,r13,_PAGE_ACCESSED@h
|
|
#else
|
|
li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
|
|
#endif
|
|
b 4f
|
|
|
|
/* Get the PGD for the current thread */
|
|
3:
|
|
mfspr r11,SPRN_SPRG_THREAD
|
|
lwz r11,PGDIR(r11)
|
|
|
|
/* Make up the required permissions for user code */
|
|
#ifdef CONFIG_PTE_64BIT
|
|
li r13,_PAGE_PRESENT | _PAGE_BAP_UX
|
|
oris r13,r13,_PAGE_ACCESSED@h
|
|
#else
|
|
li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
|
|
#endif
|
|
|
|
4:
|
|
FIND_PTE
|
|
andc. r13,r13,r11 /* Check permission */
|
|
|
|
#ifdef CONFIG_PTE_64BIT
|
|
#ifdef CONFIG_SMP
|
|
subf r13,r11,r12 /* create false data dep */
|
|
lwzx r13,r11,r13 /* Get upper pte bits */
|
|
#else
|
|
lwz r13,0(r12) /* Get upper pte bits */
|
|
#endif
|
|
#endif
|
|
|
|
bne 2f /* Bail if permission mismach */
|
|
|
|
/* Jump to common TLB load point */
|
|
b finish_tlb_load
|
|
|
|
2:
|
|
/* The bailout. Restore registers to pre-exception conditions
|
|
* and call the heavyweights to help us out.
|
|
*/
|
|
mfspr r10, SPRN_SPRG_THREAD
|
|
lwz r11, THREAD_NORMSAVE(3)(r10)
|
|
mtcr r11
|
|
lwz r13, THREAD_NORMSAVE(2)(r10)
|
|
lwz r12, THREAD_NORMSAVE(1)(r10)
|
|
lwz r11, THREAD_NORMSAVE(0)(r10)
|
|
mfspr r10, SPRN_SPRG_RSCRATCH0
|
|
b InstructionStorage
|
|
|
|
#ifdef CONFIG_SPE
|
|
/* SPE Unavailable */
|
|
START_EXCEPTION(SPEUnavailable)
|
|
NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
|
|
bne load_up_spe
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
EXC_XFER_EE_LITE(0x2010, KernelSPE)
|
|
#else
|
|
EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
|
|
unknown_exception, EXC_XFER_EE)
|
|
#endif /* CONFIG_SPE */
|
|
|
|
/* SPE Floating Point Data */
|
|
#ifdef CONFIG_SPE
|
|
EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData, \
|
|
SPEFloatingPointException, EXC_XFER_EE);
|
|
|
|
/* SPE Floating Point Round */
|
|
EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
|
|
SPEFloatingPointRoundException, EXC_XFER_EE)
|
|
#else
|
|
EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, \
|
|
unknown_exception, EXC_XFER_EE)
|
|
EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
|
|
unknown_exception, EXC_XFER_EE)
|
|
#endif /* CONFIG_SPE */
|
|
|
|
/* Performance Monitor */
|
|
EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
|
|
performance_monitor_exception, EXC_XFER_STD)
|
|
|
|
EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
|
|
|
|
CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
|
|
CriticalDoorbell, unknown_exception)
|
|
|
|
/* Debug Interrupt */
|
|
DEBUG_DEBUG_EXCEPTION
|
|
DEBUG_CRIT_EXCEPTION
|
|
|
|
GUEST_DOORBELL_EXCEPTION
|
|
|
|
CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
|
|
unknown_exception)
|
|
|
|
/* Hypercall */
|
|
EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_EE)
|
|
|
|
/* Embedded Hypervisor Privilege */
|
|
EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE)
|
|
|
|
/*
|
|
* Local functions
|
|
*/
|
|
|
|
/*
|
|
* Both the instruction and data TLB miss get to this
|
|
* point to load the TLB.
|
|
* r10 - tsize encoding (if HUGETLB_PAGE) or available to use
|
|
* r11 - TLB (info from Linux PTE)
|
|
* r12 - available to use
|
|
* r13 - upper bits of PTE (if PTE_64BIT) or available to use
|
|
* CR5 - results of addr >= PAGE_OFFSET
|
|
* MAS0, MAS1 - loaded with proper value when we get here
|
|
* MAS2, MAS3 - will need additional info from Linux PTE
|
|
* Upon exit, we reload everything and RFI.
|
|
*/
|
|
finish_tlb_load:
|
|
#ifdef CONFIG_HUGETLB_PAGE
|
|
cmpwi 6, r10, 0 /* check for huge page */
|
|
beq 6, finish_tlb_load_cont /* !huge */
|
|
|
|
/* Alas, we need more scratch registers for hugepages */
|
|
mfspr r12, SPRN_SPRG_THREAD
|
|
stw r14, THREAD_NORMSAVE(4)(r12)
|
|
stw r15, THREAD_NORMSAVE(5)(r12)
|
|
stw r16, THREAD_NORMSAVE(6)(r12)
|
|
stw r17, THREAD_NORMSAVE(7)(r12)
|
|
|
|
/* Get the next_tlbcam_idx percpu var */
|
|
#ifdef CONFIG_SMP
|
|
lwz r12, THREAD_INFO-THREAD(r12)
|
|
lwz r15, TI_CPU(r12)
|
|
lis r14, __per_cpu_offset@h
|
|
ori r14, r14, __per_cpu_offset@l
|
|
rlwinm r15, r15, 2, 0, 29
|
|
lwzx r16, r14, r15
|
|
#else
|
|
li r16, 0
|
|
#endif
|
|
lis r17, next_tlbcam_idx@h
|
|
ori r17, r17, next_tlbcam_idx@l
|
|
add r17, r17, r16 /* r17 = *next_tlbcam_idx */
|
|
lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
|
|
|
|
lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
|
|
rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
|
|
mtspr SPRN_MAS0, r14
|
|
|
|
/* Extract TLB1CFG(NENTRY) */
|
|
mfspr r16, SPRN_TLB1CFG
|
|
andi. r16, r16, 0xfff
|
|
|
|
/* Update next_tlbcam_idx, wrapping when necessary */
|
|
addi r15, r15, 1
|
|
cmpw r15, r16
|
|
blt 100f
|
|
lis r14, tlbcam_index@h
|
|
ori r14, r14, tlbcam_index@l
|
|
lwz r15, 0(r14)
|
|
100: stw r15, 0(r17)
|
|
|
|
/*
|
|
* Calc MAS1_TSIZE from r10 (which has pshift encoded)
|
|
* tlb_enc = (pshift - 10).
|
|
*/
|
|
subi r15, r10, 10
|
|
mfspr r16, SPRN_MAS1
|
|
rlwimi r16, r15, 7, 20, 24
|
|
mtspr SPRN_MAS1, r16
|
|
|
|
/* copy the pshift for use later */
|
|
mr r14, r10
|
|
|
|
/* fall through */
|
|
|
|
#endif /* CONFIG_HUGETLB_PAGE */
|
|
|
|
/*
|
|
* We set execute, because we don't have the granularity to
|
|
* properly set this at the page level (Linux problem).
|
|
* Many of these bits are software only. Bits we don't set
|
|
* here we (properly should) assume have the appropriate value.
|
|
*/
|
|
finish_tlb_load_cont:
|
|
#ifdef CONFIG_PTE_64BIT
|
|
rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
|
|
andi. r10, r11, _PAGE_DIRTY
|
|
bne 1f
|
|
li r10, MAS3_SW | MAS3_UW
|
|
andc r12, r12, r10
|
|
1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
|
|
rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
|
|
2: mtspr SPRN_MAS3, r12
|
|
BEGIN_MMU_FTR_SECTION
|
|
srwi r10, r13, 12 /* grab RPN[12:31] */
|
|
mtspr SPRN_MAS7, r10
|
|
END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
|
|
#else
|
|
li r10, (_PAGE_EXEC | _PAGE_PRESENT)
|
|
mr r13, r11
|
|
rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
|
|
and r12, r11, r10
|
|
andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
|
|
slwi r10, r12, 1
|
|
or r10, r10, r12
|
|
iseleq r12, r12, r10
|
|
rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
|
|
mtspr SPRN_MAS3, r13
|
|
#endif
|
|
|
|
mfspr r12, SPRN_MAS2
|
|
#ifdef CONFIG_PTE_64BIT
|
|
rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
|
|
#else
|
|
rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
|
|
#endif
|
|
#ifdef CONFIG_HUGETLB_PAGE
|
|
beq 6, 3f /* don't mask if page isn't huge */
|
|
li r13, 1
|
|
slw r13, r13, r14
|
|
subi r13, r13, 1
|
|
rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
|
|
andc r12, r12, r13 /* mask off ea bits within the page */
|
|
#endif
|
|
3: mtspr SPRN_MAS2, r12
|
|
|
|
#ifdef CONFIG_E200
|
|
/* Round robin TLB1 entries assignment */
|
|
mfspr r12, SPRN_MAS0
|
|
|
|
/* Extract TLB1CFG(NENTRY) */
|
|
mfspr r11, SPRN_TLB1CFG
|
|
andi. r11, r11, 0xfff
|
|
|
|
/* Extract MAS0(NV) */
|
|
andi. r13, r12, 0xfff
|
|
addi r13, r13, 1
|
|
cmpw 0, r13, r11
|
|
addi r12, r12, 1
|
|
|
|
/* check if we need to wrap */
|
|
blt 7f
|
|
|
|
/* wrap back to first free tlbcam entry */
|
|
lis r13, tlbcam_index@ha
|
|
lwz r13, tlbcam_index@l(r13)
|
|
rlwimi r12, r13, 0, 20, 31
|
|
7:
|
|
mtspr SPRN_MAS0,r12
|
|
#endif /* CONFIG_E200 */
|
|
|
|
tlb_write_entry:
|
|
tlbwe
|
|
|
|
/* Done...restore registers and get out of here. */
|
|
mfspr r10, SPRN_SPRG_THREAD
|
|
#ifdef CONFIG_HUGETLB_PAGE
|
|
beq 6, 8f /* skip restore for 4k page faults */
|
|
lwz r14, THREAD_NORMSAVE(4)(r10)
|
|
lwz r15, THREAD_NORMSAVE(5)(r10)
|
|
lwz r16, THREAD_NORMSAVE(6)(r10)
|
|
lwz r17, THREAD_NORMSAVE(7)(r10)
|
|
#endif
|
|
8: lwz r11, THREAD_NORMSAVE(3)(r10)
|
|
mtcr r11
|
|
lwz r13, THREAD_NORMSAVE(2)(r10)
|
|
lwz r12, THREAD_NORMSAVE(1)(r10)
|
|
lwz r11, THREAD_NORMSAVE(0)(r10)
|
|
mfspr r10, SPRN_SPRG_RSCRATCH0
|
|
rfi /* Force context change */
|
|
|
|
#ifdef CONFIG_SPE
|
|
/* Note that the SPE support is closely modeled after the AltiVec
|
|
* support. Changes to one are likely to be applicable to the
|
|
* other! */
|
|
load_up_spe:
|
|
/*
|
|
* Disable SPE for the task which had SPE previously,
|
|
* and save its SPE registers in its thread_struct.
|
|
* Enables SPE for use in the kernel on return.
|
|
* On SMP we know the SPE units are free, since we give it up every
|
|
* switch. -- Kumar
|
|
*/
|
|
mfmsr r5
|
|
oris r5,r5,MSR_SPE@h
|
|
mtmsr r5 /* enable use of SPE now */
|
|
isync
|
|
/*
|
|
* For SMP, we don't do lazy SPE switching because it just gets too
|
|
* horrendously complex, especially when a task switches from one CPU
|
|
* to another. Instead we call giveup_spe in switch_to.
|
|
*/
|
|
#ifndef CONFIG_SMP
|
|
lis r3,last_task_used_spe@ha
|
|
lwz r4,last_task_used_spe@l(r3)
|
|
cmpi 0,r4,0
|
|
beq 1f
|
|
addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
|
|
SAVE_32EVRS(0,r10,r4,THREAD_EVR0)
|
|
evxor evr10, evr10, evr10 /* clear out evr10 */
|
|
evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
|
|
li r5,THREAD_ACC
|
|
evstddx evr10, r4, r5 /* save off accumulator */
|
|
lwz r5,PT_REGS(r4)
|
|
lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
|
|
lis r10,MSR_SPE@h
|
|
andc r4,r4,r10 /* disable SPE for previous task */
|
|
stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
|
|
1:
|
|
#endif /* !CONFIG_SMP */
|
|
/* enable use of SPE after return */
|
|
oris r9,r9,MSR_SPE@h
|
|
mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
|
|
li r4,1
|
|
li r10,THREAD_ACC
|
|
stw r4,THREAD_USED_SPE(r5)
|
|
evlddx evr4,r10,r5
|
|
evmra evr4,evr4
|
|
REST_32EVRS(0,r10,r5,THREAD_EVR0)
|
|
#ifndef CONFIG_SMP
|
|
subi r4,r5,THREAD
|
|
stw r4,last_task_used_spe@l(r3)
|
|
#endif /* !CONFIG_SMP */
|
|
/* restore registers and return */
|
|
2: REST_4GPRS(3, r11)
|
|
lwz r10,_CCR(r11)
|
|
REST_GPR(1, r11)
|
|
mtcr r10
|
|
lwz r10,_LINK(r11)
|
|
mtlr r10
|
|
REST_GPR(10, r11)
|
|
mtspr SPRN_SRR1,r9
|
|
mtspr SPRN_SRR0,r12
|
|
REST_GPR(9, r11)
|
|
REST_GPR(12, r11)
|
|
lwz r11,GPR11(r11)
|
|
rfi
|
|
|
|
/*
|
|
* SPE unavailable trap from kernel - print a message, but let
|
|
* the task use SPE in the kernel until it returns to user mode.
|
|
*/
|
|
KernelSPE:
|
|
lwz r3,_MSR(r1)
|
|
oris r3,r3,MSR_SPE@h
|
|
stw r3,_MSR(r1) /* enable use of SPE after return */
|
|
#ifdef CONFIG_PRINTK
|
|
lis r3,87f@h
|
|
ori r3,r3,87f@l
|
|
mr r4,r2 /* current */
|
|
lwz r5,_NIP(r1)
|
|
bl printk
|
|
#endif
|
|
b ret_from_except
|
|
#ifdef CONFIG_PRINTK
|
|
87: .string "SPE used in kernel (task=%p, pc=%x) \n"
|
|
#endif
|
|
.align 4,0
|
|
|
|
#endif /* CONFIG_SPE */
|
|
|
|
/*
|
|
* Global functions
|
|
*/
|
|
|
|
/* Adjust or setup IVORs for e200 */
|
|
_GLOBAL(__setup_e200_ivors)
|
|
li r3,DebugDebug@l
|
|
mtspr SPRN_IVOR15,r3
|
|
li r3,SPEUnavailable@l
|
|
mtspr SPRN_IVOR32,r3
|
|
li r3,SPEFloatingPointData@l
|
|
mtspr SPRN_IVOR33,r3
|
|
li r3,SPEFloatingPointRound@l
|
|
mtspr SPRN_IVOR34,r3
|
|
sync
|
|
blr
|
|
|
|
/* Adjust or setup IVORs for e500v1/v2 */
|
|
_GLOBAL(__setup_e500_ivors)
|
|
li r3,DebugCrit@l
|
|
mtspr SPRN_IVOR15,r3
|
|
li r3,SPEUnavailable@l
|
|
mtspr SPRN_IVOR32,r3
|
|
li r3,SPEFloatingPointData@l
|
|
mtspr SPRN_IVOR33,r3
|
|
li r3,SPEFloatingPointRound@l
|
|
mtspr SPRN_IVOR34,r3
|
|
li r3,PerformanceMonitor@l
|
|
mtspr SPRN_IVOR35,r3
|
|
sync
|
|
blr
|
|
|
|
/* Adjust or setup IVORs for e500mc */
|
|
_GLOBAL(__setup_e500mc_ivors)
|
|
li r3,DebugDebug@l
|
|
mtspr SPRN_IVOR15,r3
|
|
li r3,PerformanceMonitor@l
|
|
mtspr SPRN_IVOR35,r3
|
|
li r3,Doorbell@l
|
|
mtspr SPRN_IVOR36,r3
|
|
li r3,CriticalDoorbell@l
|
|
mtspr SPRN_IVOR37,r3
|
|
|
|
/*
|
|
* We only want to touch IVOR38-41 if we're running on hardware
|
|
* that supports category E.HV. The architectural way to determine
|
|
* this is MMUCFG[LPIDSIZE].
|
|
*/
|
|
mfspr r3, SPRN_MMUCFG
|
|
andis. r3, r3, MMUCFG_LPIDSIZE@h
|
|
beq no_hv
|
|
li r3,GuestDoorbell@l
|
|
mtspr SPRN_IVOR38,r3
|
|
li r3,CriticalGuestDoorbell@l
|
|
mtspr SPRN_IVOR39,r3
|
|
li r3,Hypercall@l
|
|
mtspr SPRN_IVOR40,r3
|
|
li r3,Ehvpriv@l
|
|
mtspr SPRN_IVOR41,r3
|
|
skip_hv_ivors:
|
|
sync
|
|
blr
|
|
no_hv:
|
|
lwz r3, CPU_SPEC_FEATURES(r5)
|
|
rlwinm r3, r3, 0, ~CPU_FTR_EMB_HV
|
|
stw r3, CPU_SPEC_FEATURES(r5)
|
|
b skip_hv_ivors
|
|
|
|
#ifdef CONFIG_SPE
|
|
/*
|
|
* extern void giveup_spe(struct task_struct *prev)
|
|
*
|
|
*/
|
|
_GLOBAL(giveup_spe)
|
|
mfmsr r5
|
|
oris r5,r5,MSR_SPE@h
|
|
mtmsr r5 /* enable use of SPE now */
|
|
isync
|
|
cmpi 0,r3,0
|
|
beqlr- /* if no previous owner, done */
|
|
addi r3,r3,THREAD /* want THREAD of task */
|
|
lwz r5,PT_REGS(r3)
|
|
cmpi 0,r5,0
|
|
SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
|
|
evxor evr6, evr6, evr6 /* clear out evr6 */
|
|
evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
|
|
li r4,THREAD_ACC
|
|
evstddx evr6, r4, r3 /* save off accumulator */
|
|
beq 1f
|
|
lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
|
|
lis r3,MSR_SPE@h
|
|
andc r4,r4,r3 /* disable SPE for previous task */
|
|
stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
|
|
1:
|
|
#ifndef CONFIG_SMP
|
|
li r5,0
|
|
lis r4,last_task_used_spe@ha
|
|
stw r5,last_task_used_spe@l(r4)
|
|
#endif /* !CONFIG_SMP */
|
|
blr
|
|
#endif /* CONFIG_SPE */
|
|
|
|
/*
|
|
* extern void giveup_fpu(struct task_struct *prev)
|
|
*
|
|
* Not all FSL Book-E cores have an FPU
|
|
*/
|
|
#ifndef CONFIG_PPC_FPU
|
|
_GLOBAL(giveup_fpu)
|
|
blr
|
|
#endif
|
|
|
|
/*
|
|
* extern void abort(void)
|
|
*
|
|
* At present, this routine just applies a system reset.
|
|
*/
|
|
_GLOBAL(abort)
|
|
li r13,0
|
|
mtspr SPRN_DBCR0,r13 /* disable all debug events */
|
|
isync
|
|
mfmsr r13
|
|
ori r13,r13,MSR_DE@l /* Enable Debug Events */
|
|
mtmsr r13
|
|
isync
|
|
mfspr r13,SPRN_DBCR0
|
|
lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
|
|
mtspr SPRN_DBCR0,r13
|
|
isync
|
|
|
|
_GLOBAL(set_context)
|
|
|
|
#ifdef CONFIG_BDI_SWITCH
|
|
/* Context switch the PTE pointer for the Abatron BDI2000.
|
|
* The PGDIR is the second parameter.
|
|
*/
|
|
lis r5, abatron_pteptrs@h
|
|
ori r5, r5, abatron_pteptrs@l
|
|
stw r4, 0x4(r5)
|
|
#endif
|
|
mtspr SPRN_PID,r3
|
|
isync /* Force context change */
|
|
blr
|
|
|
|
_GLOBAL(flush_dcache_L1)
|
|
mfspr r3,SPRN_L1CFG0
|
|
|
|
rlwinm r5,r3,9,3 /* Extract cache block size */
|
|
twlgti r5,1 /* Only 32 and 64 byte cache blocks
|
|
* are currently defined.
|
|
*/
|
|
li r4,32
|
|
subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
|
|
* log2(number of ways)
|
|
*/
|
|
slw r5,r4,r5 /* r5 = cache block size */
|
|
|
|
rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
|
|
mulli r7,r7,13 /* An 8-way cache will require 13
|
|
* loads per set.
|
|
*/
|
|
slw r7,r7,r6
|
|
|
|
/* save off HID0 and set DCFA */
|
|
mfspr r8,SPRN_HID0
|
|
ori r9,r8,HID0_DCFA@l
|
|
mtspr SPRN_HID0,r9
|
|
isync
|
|
|
|
lis r4,KERNELBASE@h
|
|
mtctr r7
|
|
|
|
1: lwz r3,0(r4) /* Load... */
|
|
add r4,r4,r5
|
|
bdnz 1b
|
|
|
|
msync
|
|
lis r4,KERNELBASE@h
|
|
mtctr r7
|
|
|
|
1: dcbf 0,r4 /* ...and flush. */
|
|
add r4,r4,r5
|
|
bdnz 1b
|
|
|
|
/* restore HID0 */
|
|
mtspr SPRN_HID0,r8
|
|
isync
|
|
|
|
blr
|
|
|
|
#ifdef CONFIG_SMP
|
|
/* When we get here, r24 needs to hold the CPU # */
|
|
.globl __secondary_start
|
|
__secondary_start:
|
|
lis r3,__secondary_hold_acknowledge@h
|
|
ori r3,r3,__secondary_hold_acknowledge@l
|
|
stw r24,0(r3)
|
|
|
|
li r3,0
|
|
mr r4,r24 /* Why? */
|
|
bl call_setup_cpu
|
|
|
|
lis r3,tlbcam_index@ha
|
|
lwz r3,tlbcam_index@l(r3)
|
|
mtctr r3
|
|
li r26,0 /* r26 safe? */
|
|
|
|
/* Load each CAM entry */
|
|
1: mr r3,r26
|
|
bl loadcam_entry
|
|
addi r26,r26,1
|
|
bdnz 1b
|
|
|
|
/* get current_thread_info and current */
|
|
lis r1,secondary_ti@ha
|
|
lwz r1,secondary_ti@l(r1)
|
|
lwz r2,TI_TASK(r1)
|
|
|
|
/* stack */
|
|
addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
|
|
li r0,0
|
|
stw r0,0(r1)
|
|
|
|
/* ptr to current thread */
|
|
addi r4,r2,THREAD /* address of our thread_struct */
|
|
mtspr SPRN_SPRG_THREAD,r4
|
|
|
|
/* Setup the defaults for TLB entries */
|
|
li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
|
|
mtspr SPRN_MAS4,r4
|
|
|
|
/* Jump to start_secondary */
|
|
lis r4,MSR_KERNEL@h
|
|
ori r4,r4,MSR_KERNEL@l
|
|
lis r3,start_secondary@h
|
|
ori r3,r3,start_secondary@l
|
|
mtspr SPRN_SRR0,r3
|
|
mtspr SPRN_SRR1,r4
|
|
sync
|
|
rfi
|
|
sync
|
|
|
|
.globl __secondary_hold_acknowledge
|
|
__secondary_hold_acknowledge:
|
|
.long -1
|
|
#endif
|
|
|
|
/*
|
|
* We put a few things here that have to be page-aligned. This stuff
|
|
* goes at the beginning of the data segment, which is page-aligned.
|
|
*/
|
|
.data
|
|
.align 12
|
|
.globl sdata
|
|
sdata:
|
|
.globl empty_zero_page
|
|
empty_zero_page:
|
|
.space 4096
|
|
.globl swapper_pg_dir
|
|
swapper_pg_dir:
|
|
.space PGD_TABLE_SIZE
|
|
|
|
/*
|
|
* Room for two PTE pointers, usually the kernel and current user pointers
|
|
* to their respective root page table.
|
|
*/
|
|
abatron_pteptrs:
|
|
.space 8
|