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cd99ddbea2
In TLB miss handlers, updating the perf counter is only useful when performing a perf analysis. As it has a noticeable overhead, let's only do it when needed. In order to do so, the exit of the miss handlers will be patched when starting/stopping 'perf': the first register restore instruction of each exit point will be replaced by a jump to the counting code. Once this is done, CONFIG_PPC_8xx_PERF_EVENT becomes useless as this feature doesn't add any overhead. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
218 lines
5.4 KiB
C
218 lines
5.4 KiB
C
/*
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* Performance event support - PPC 8xx
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*
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* Copyright 2016 Christophe Leroy, CS Systemes d'Information
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/perf_event.h>
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#include <linux/percpu.h>
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#include <linux/hardirq.h>
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#include <asm/pmc.h>
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#include <asm/machdep.h>
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#include <asm/firmware.h>
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#include <asm/ptrace.h>
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#include <asm/code-patching.h>
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#define PERF_8xx_ID_CPU_CYCLES 1
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#define PERF_8xx_ID_HW_INSTRUCTIONS 2
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#define PERF_8xx_ID_ITLB_LOAD_MISS 3
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#define PERF_8xx_ID_DTLB_LOAD_MISS 4
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#define C(x) PERF_COUNT_HW_CACHE_##x
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#define DTLB_LOAD_MISS (C(DTLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16))
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#define ITLB_LOAD_MISS (C(ITLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16))
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extern unsigned long itlb_miss_counter, dtlb_miss_counter;
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extern atomic_t instruction_counter;
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extern unsigned int itlb_miss_perf, dtlb_miss_perf;
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extern unsigned int itlb_miss_exit_1, itlb_miss_exit_2;
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extern unsigned int dtlb_miss_exit_1, dtlb_miss_exit_2, dtlb_miss_exit_3;
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static atomic_t insn_ctr_ref;
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static atomic_t itlb_miss_ref;
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static atomic_t dtlb_miss_ref;
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static s64 get_insn_ctr(void)
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{
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int ctr;
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unsigned long counta;
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do {
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ctr = atomic_read(&instruction_counter);
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counta = mfspr(SPRN_COUNTA);
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} while (ctr != atomic_read(&instruction_counter));
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return ((s64)ctr << 16) | (counta >> 16);
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}
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static int event_type(struct perf_event *event)
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{
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switch (event->attr.type) {
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case PERF_TYPE_HARDWARE:
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if (event->attr.config == PERF_COUNT_HW_CPU_CYCLES)
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return PERF_8xx_ID_CPU_CYCLES;
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if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS)
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return PERF_8xx_ID_HW_INSTRUCTIONS;
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break;
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case PERF_TYPE_HW_CACHE:
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if (event->attr.config == ITLB_LOAD_MISS)
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return PERF_8xx_ID_ITLB_LOAD_MISS;
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if (event->attr.config == DTLB_LOAD_MISS)
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return PERF_8xx_ID_DTLB_LOAD_MISS;
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break;
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case PERF_TYPE_RAW:
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break;
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default:
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return -ENOENT;
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}
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return -EOPNOTSUPP;
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}
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static int mpc8xx_pmu_event_init(struct perf_event *event)
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{
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int type = event_type(event);
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if (type < 0)
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return type;
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return 0;
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}
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static int mpc8xx_pmu_add(struct perf_event *event, int flags)
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{
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int type = event_type(event);
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s64 val = 0;
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if (type < 0)
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return type;
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switch (type) {
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case PERF_8xx_ID_CPU_CYCLES:
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val = get_tb();
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break;
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case PERF_8xx_ID_HW_INSTRUCTIONS:
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if (atomic_inc_return(&insn_ctr_ref) == 1)
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mtspr(SPRN_ICTRL, 0xc0080007);
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val = get_insn_ctr();
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break;
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case PERF_8xx_ID_ITLB_LOAD_MISS:
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if (atomic_inc_return(&itlb_miss_ref) == 1) {
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unsigned long target = (unsigned long)&itlb_miss_perf;
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patch_branch(&itlb_miss_exit_1, target, 0);
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#ifndef CONFIG_PIN_TLB_TEXT
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patch_branch(&itlb_miss_exit_2, target, 0);
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#endif
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}
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val = itlb_miss_counter;
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break;
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case PERF_8xx_ID_DTLB_LOAD_MISS:
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if (atomic_inc_return(&dtlb_miss_ref) == 1) {
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unsigned long target = (unsigned long)&dtlb_miss_perf;
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patch_branch(&dtlb_miss_exit_1, target, 0);
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patch_branch(&dtlb_miss_exit_2, target, 0);
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patch_branch(&dtlb_miss_exit_3, target, 0);
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}
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val = dtlb_miss_counter;
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break;
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}
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local64_set(&event->hw.prev_count, val);
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return 0;
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}
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static void mpc8xx_pmu_read(struct perf_event *event)
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{
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int type = event_type(event);
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s64 prev, val = 0, delta = 0;
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if (type < 0)
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return;
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do {
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prev = local64_read(&event->hw.prev_count);
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switch (type) {
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case PERF_8xx_ID_CPU_CYCLES:
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val = get_tb();
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delta = 16 * (val - prev);
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break;
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case PERF_8xx_ID_HW_INSTRUCTIONS:
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val = get_insn_ctr();
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delta = prev - val;
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if (delta < 0)
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delta += 0x1000000000000LL;
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break;
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case PERF_8xx_ID_ITLB_LOAD_MISS:
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val = itlb_miss_counter;
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delta = (s64)((s32)val - (s32)prev);
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break;
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case PERF_8xx_ID_DTLB_LOAD_MISS:
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val = dtlb_miss_counter;
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delta = (s64)((s32)val - (s32)prev);
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break;
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}
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} while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
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local64_add(delta, &event->count);
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}
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static void mpc8xx_pmu_del(struct perf_event *event, int flags)
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{
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/* mfspr r10, SPRN_SPRG_SCRATCH0 */
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unsigned int insn = PPC_INST_MFSPR | __PPC_RS(R10) |
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__PPC_SPR(SPRN_SPRG_SCRATCH0);
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mpc8xx_pmu_read(event);
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/* If it was the last user, stop counting to avoid useles overhead */
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switch (event_type(event)) {
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case PERF_8xx_ID_CPU_CYCLES:
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break;
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case PERF_8xx_ID_HW_INSTRUCTIONS:
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if (atomic_dec_return(&insn_ctr_ref) == 0)
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mtspr(SPRN_ICTRL, 7);
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break;
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case PERF_8xx_ID_ITLB_LOAD_MISS:
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if (atomic_dec_return(&itlb_miss_ref) == 0) {
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patch_instruction(&itlb_miss_exit_1, insn);
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#ifndef CONFIG_PIN_TLB_TEXT
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patch_instruction(&itlb_miss_exit_2, insn);
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#endif
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}
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break;
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case PERF_8xx_ID_DTLB_LOAD_MISS:
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if (atomic_dec_return(&dtlb_miss_ref) == 0) {
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patch_instruction(&dtlb_miss_exit_1, insn);
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patch_instruction(&dtlb_miss_exit_2, insn);
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patch_instruction(&dtlb_miss_exit_3, insn);
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}
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break;
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}
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}
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static struct pmu mpc8xx_pmu = {
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.event_init = mpc8xx_pmu_event_init,
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.add = mpc8xx_pmu_add,
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.del = mpc8xx_pmu_del,
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.read = mpc8xx_pmu_read,
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.capabilities = PERF_PMU_CAP_NO_INTERRUPT |
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PERF_PMU_CAP_NO_NMI,
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};
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static int init_mpc8xx_pmu(void)
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{
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mtspr(SPRN_ICTRL, 7);
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mtspr(SPRN_CMPA, 0);
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mtspr(SPRN_COUNTA, 0xffff);
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return perf_pmu_register(&mpc8xx_pmu, "cpu", PERF_TYPE_RAW);
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}
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early_initcall(init_mpc8xx_pmu);
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