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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-29 23:36:45 +07:00
010dc8af8f
Two problems exist in the current i.MX5 pm suspend/resume and idle functions. The first is the current i.MX5 suspend routine will call tzic_enable_wake(1) to set wake source, this will set all enabled irq as wake source rather than those wake capable. The second is i.MX5 idle will call mx5_cpu_lp_set() to prepare enter low power mode, but it forgets to call wfi instruction to enter this mode. To fix these two problems, using generic irq chip pm interface and modify function imx5_idle(). [Tested by Shawn Guo on imx51 babbage board. Tested by Hui Wang on imx51 pdk board.] Signed-off-by: Hui Wang <jason77.wang@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
83 lines
2.4 KiB
C
83 lines
2.4 KiB
C
/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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#include "crm_regs.h"
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/* set cpu low power mode before WFI instruction. This function is called
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* mx5 because it can be used for mx50, mx51, and mx53.*/
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void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
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{
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u32 plat_lpc, arm_srpgcr, ccm_clpcr;
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u32 empgc0, empgc1;
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int stop_mode = 0;
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/* always allow platform to issue a deep sleep mode request */
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plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
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~(MXC_CORTEXA8_PLAT_LPC_DSM);
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ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
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arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
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empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
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empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
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switch (mode) {
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case WAIT_CLOCKED:
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break;
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case WAIT_UNCLOCKED:
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ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
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break;
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case WAIT_UNCLOCKED_POWER_OFF:
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case STOP_POWER_OFF:
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plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM
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| MXC_CORTEXA8_PLAT_LPC_DBG_DSM;
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if (mode == WAIT_UNCLOCKED_POWER_OFF) {
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ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET;
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ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY;
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ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS;
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stop_mode = 0;
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} else {
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ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
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ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET;
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ccm_clpcr |= MXC_CCM_CLPCR_VSTBY;
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ccm_clpcr |= MXC_CCM_CLPCR_SBYOS;
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stop_mode = 1;
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}
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arm_srpgcr |= MXC_SRPGCR_PCR;
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break;
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case STOP_POWER_ON:
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ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
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break;
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default:
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printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode);
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return;
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}
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__raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
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__raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
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__raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
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/* Enable NEON SRPG for all but MX50TO1.0. */
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if (mx50_revision() != IMX_CHIP_REVISION_1_0)
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__raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
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if (stop_mode) {
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empgc0 |= MXC_SRPGCR_PCR;
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empgc1 |= MXC_SRPGCR_PCR;
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__raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
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__raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
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}
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}
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