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980a01c9bf
This patch adds earlier initialization of spi_device.mode, as needed on boards using nondefault chipselect polarity. An example would be ones using the RS5C348 RTC without an external signal inverter between the RTC chipselect and the SPI controller. Without this mechanism, the first setup() call for that chip would wrongly enable chips, corrupting transfers to/from other chips sharing that SPI bus. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
684 lines
23 KiB
C
684 lines
23 KiB
C
/*
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* Copyright (C) 2005 David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __LINUX_SPI_H
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#define __LINUX_SPI_H
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/*
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* INTERFACES between SPI master-side drivers and SPI infrastructure.
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* (There's no SPI slave support for Linux yet...)
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*/
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extern struct bus_type spi_bus_type;
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/**
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* struct spi_device - Master side proxy for an SPI slave device
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* @dev: Driver model representation of the device.
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* @master: SPI controller used with the device.
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* @max_speed_hz: Maximum clock rate to be used with this chip
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* (on this board); may be changed by the device's driver.
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* The spi_transfer.speed_hz can override this for each transfer.
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* @chip-select: Chipselect, distinguishing chips handled by "master".
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* @mode: The spi mode defines how data is clocked out and in.
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* This may be changed by the device's driver.
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* The "active low" default for chipselect mode can be overridden,
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* as can the "MSB first" default for each word in a transfer.
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* @bits_per_word: Data transfers involve one or more words; word sizes
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* like eight or 12 bits are common. In-memory wordsizes are
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* powers of two bytes (e.g. 20 bit samples use 32 bits).
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* This may be changed by the device's driver, or left at the
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* default (0) indicating protocol words are eight bit bytes.
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* The spi_transfer.bits_per_word can override this for each transfer.
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* @irq: Negative, or the number passed to request_irq() to receive
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* interrupts from this device.
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* @controller_state: Controller's runtime state
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* @controller_data: Board-specific definitions for controller, such as
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* FIFO initialization parameters; from board_info.controller_data
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*
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* An spi_device is used to interchange data between an SPI slave
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* (usually a discrete chip) and CPU memory.
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*
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* In "dev", the platform_data is used to hold information about this
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* device that's meaningful to the device's protocol driver, but not
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* to its controller. One example might be an identifier for a chip
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* variant with slightly different functionality.
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*/
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struct spi_device {
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struct device dev;
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struct spi_master *master;
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u32 max_speed_hz;
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u8 chip_select;
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u8 mode;
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#define SPI_CPHA 0x01 /* clock phase */
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#define SPI_CPOL 0x02 /* clock polarity */
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#define SPI_MODE_0 (0|0) /* (original MicroWire) */
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#define SPI_MODE_1 (0|SPI_CPHA)
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#define SPI_MODE_2 (SPI_CPOL|0)
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#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
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#define SPI_CS_HIGH 0x04 /* chipselect active high? */
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#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
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u8 bits_per_word;
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int irq;
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void *controller_state;
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void *controller_data;
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const char *modalias;
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// likely need more hooks for more protocol options affecting how
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// the controller talks to each chip, like:
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// - memory packing (12 bit samples into low bits, others zeroed)
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// - priority
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// - drop chipselect after each word
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// - chipselect delays
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// - ...
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};
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static inline struct spi_device *to_spi_device(struct device *dev)
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{
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return dev ? container_of(dev, struct spi_device, dev) : NULL;
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}
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/* most drivers won't need to care about device refcounting */
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static inline struct spi_device *spi_dev_get(struct spi_device *spi)
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{
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return (spi && get_device(&spi->dev)) ? spi : NULL;
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}
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static inline void spi_dev_put(struct spi_device *spi)
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{
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if (spi)
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put_device(&spi->dev);
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}
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/* ctldata is for the bus_master driver's runtime state */
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static inline void *spi_get_ctldata(struct spi_device *spi)
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{
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return spi->controller_state;
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}
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static inline void spi_set_ctldata(struct spi_device *spi, void *state)
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{
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spi->controller_state = state;
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}
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struct spi_message;
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struct spi_driver {
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int (*probe)(struct spi_device *spi);
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int (*remove)(struct spi_device *spi);
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void (*shutdown)(struct spi_device *spi);
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int (*suspend)(struct spi_device *spi, pm_message_t mesg);
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int (*resume)(struct spi_device *spi);
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struct device_driver driver;
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};
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static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
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{
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return drv ? container_of(drv, struct spi_driver, driver) : NULL;
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}
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extern int spi_register_driver(struct spi_driver *sdrv);
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static inline void spi_unregister_driver(struct spi_driver *sdrv)
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{
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if (!sdrv)
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return;
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driver_unregister(&sdrv->driver);
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}
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/**
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* struct spi_master - interface to SPI master controller
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* @cdev: class interface to this driver
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* @bus_num: board-specific (and often SOC-specific) identifier for a
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* given SPI controller.
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* @num_chipselect: chipselects are used to distinguish individual
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* SPI slaves, and are numbered from zero to num_chipselects.
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* each slave has a chipselect signal, but it's common that not
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* every chipselect is connected to a slave.
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* @setup: updates the device mode and clocking records used by a
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* device's SPI controller; protocol code may call this.
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* @transfer: adds a message to the controller's transfer queue.
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* @cleanup: frees controller-specific state
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*
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* Each SPI master controller can communicate with one or more spi_device
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* children. These make a small bus, sharing MOSI, MISO and SCK signals
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* but not chip select signals. Each device may be configured to use a
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* different clock rate, since those shared signals are ignored unless
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* the chip is selected.
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*
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* The driver for an SPI controller manages access to those devices through
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* a queue of spi_message transactions, copyin data between CPU memory and
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* an SPI slave device). For each such message it queues, it calls the
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* message's completion function when the transaction completes.
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*/
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struct spi_master {
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struct class_device cdev;
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/* other than negative (== assign one dynamically), bus_num is fully
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* board-specific. usually that simplifies to being SOC-specific.
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* example: one SOC has three SPI controllers, numbered 0..2,
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* and one board's schematics might show it using SPI-2. software
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* would normally use bus_num=2 for that controller.
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*/
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s16 bus_num;
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/* chipselects will be integral to many controllers; some others
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* might use board-specific GPIOs.
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*/
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u16 num_chipselect;
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/* setup mode and clock, etc (spi driver may call many times) */
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int (*setup)(struct spi_device *spi);
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/* bidirectional bulk transfers
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*
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* + The transfer() method may not sleep; its main role is
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* just to add the message to the queue.
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* + For now there's no remove-from-queue operation, or
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* any other request management
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* + To a given spi_device, message queueing is pure fifo
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*
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* + The master's main job is to process its message queue,
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* selecting a chip then transferring data
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* + If there are multiple spi_device children, the i/o queue
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* arbitration algorithm is unspecified (round robin, fifo,
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* priority, reservations, preemption, etc)
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*
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* + Chipselect stays active during the entire message
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* (unless modified by spi_transfer.cs_change != 0).
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* + The message transfers use clock and SPI mode parameters
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* previously established by setup() for this device
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*/
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int (*transfer)(struct spi_device *spi,
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struct spi_message *mesg);
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/* called on release() to free memory provided by spi_master */
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void (*cleanup)(const struct spi_device *spi);
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};
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static inline void *spi_master_get_devdata(struct spi_master *master)
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{
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return class_get_devdata(&master->cdev);
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}
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static inline void spi_master_set_devdata(struct spi_master *master, void *data)
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{
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class_set_devdata(&master->cdev, data);
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}
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static inline struct spi_master *spi_master_get(struct spi_master *master)
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{
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if (!master || !class_device_get(&master->cdev))
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return NULL;
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return master;
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}
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static inline void spi_master_put(struct spi_master *master)
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{
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if (master)
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class_device_put(&master->cdev);
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}
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/* the spi driver core manages memory for the spi_master classdev */
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extern struct spi_master *
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spi_alloc_master(struct device *host, unsigned size);
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extern int spi_register_master(struct spi_master *master);
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extern void spi_unregister_master(struct spi_master *master);
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extern struct spi_master *spi_busnum_to_master(u16 busnum);
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/*---------------------------------------------------------------------------*/
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/*
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* I/O INTERFACE between SPI controller and protocol drivers
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*
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* Protocol drivers use a queue of spi_messages, each transferring data
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* between the controller and memory buffers.
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*
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* The spi_messages themselves consist of a series of read+write transfer
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* segments. Those segments always read the same number of bits as they
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* write; but one or the other is easily ignored by passing a null buffer
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* pointer. (This is unlike most types of I/O API, because SPI hardware
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* is full duplex.)
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*
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* NOTE: Allocation of spi_transfer and spi_message memory is entirely
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* up to the protocol driver, which guarantees the integrity of both (as
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* well as the data buffers) for as long as the message is queued.
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*/
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/**
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* struct spi_transfer - a read/write buffer pair
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* @tx_buf: data to be written (dma-safe memory), or NULL
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* @rx_buf: data to be read (dma-safe memory), or NULL
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* @tx_dma: DMA address of tx_buf, if spi_message.is_dma_mapped
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* @rx_dma: DMA address of rx_buf, if spi_message.is_dma_mapped
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* @len: size of rx and tx buffers (in bytes)
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* @speed_hz: Select a speed other then the device default for this
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* transfer. If 0 the default (from spi_device) is used.
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* @bits_per_word: select a bits_per_word other then the device default
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* for this transfer. If 0 the default (from spi_device) is used.
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* @cs_change: affects chipselect after this transfer completes
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* @delay_usecs: microseconds to delay after this transfer before
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* (optionally) changing the chipselect status, then starting
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* the next transfer or completing this spi_message.
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* @transfer_list: transfers are sequenced through spi_message.transfers
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*
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* SPI transfers always write the same number of bytes as they read.
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* Protocol drivers should always provide rx_buf and/or tx_buf.
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* In some cases, they may also want to provide DMA addresses for
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* the data being transferred; that may reduce overhead, when the
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* underlying driver uses dma.
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*
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* If the transmit buffer is null, undefined data will be shifted out
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* while filling rx_buf. If the receive buffer is null, the data
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* shifted in will be discarded. Only "len" bytes shift out (or in).
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* It's an error to try to shift out a partial word. (For example, by
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* shifting out three bytes with word size of sixteen or twenty bits;
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* the former uses two bytes per word, the latter uses four bytes.)
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*
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* All SPI transfers start with the relevant chipselect active. Normally
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* it stays selected until after the last transfer in a message. Drivers
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* can affect the chipselect signal using cs_change:
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*
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* (i) If the transfer isn't the last one in the message, this flag is
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* used to make the chipselect briefly go inactive in the middle of the
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* message. Toggling chipselect in this way may be needed to terminate
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* a chip command, letting a single spi_message perform all of group of
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* chip transactions together.
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*
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* (ii) When the transfer is the last one in the message, the chip may
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* stay selected until the next transfer. This is purely a performance
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* hint; the controller driver may need to select a different device
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* for the next message.
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*
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* The code that submits an spi_message (and its spi_transfers)
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* to the lower layers is responsible for managing its memory.
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* Zero-initialize every field you don't set up explicitly, to
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* insulate against future API updates. After you submit a message
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* and its transfers, ignore them until its completion callback.
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*/
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struct spi_transfer {
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/* it's ok if tx_buf == rx_buf (right?)
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* for MicroWire, one buffer must be null
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* buffers must work with dma_*map_single() calls, unless
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* spi_message.is_dma_mapped reports a pre-existing mapping
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*/
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const void *tx_buf;
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void *rx_buf;
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unsigned len;
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dma_addr_t tx_dma;
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dma_addr_t rx_dma;
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unsigned cs_change:1;
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u8 bits_per_word;
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u16 delay_usecs;
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u32 speed_hz;
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struct list_head transfer_list;
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};
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/**
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* struct spi_message - one multi-segment SPI transaction
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* @transfers: list of transfer segments in this transaction
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* @spi: SPI device to which the transaction is queued
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* @is_dma_mapped: if true, the caller provided both dma and cpu virtual
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* addresses for each transfer buffer
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* @complete: called to report transaction completions
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* @context: the argument to complete() when it's called
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* @actual_length: the total number of bytes that were transferred in all
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* successful segments
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* @status: zero for success, else negative errno
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* @queue: for use by whichever driver currently owns the message
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* @state: for use by whichever driver currently owns the message
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*
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* An spi_message is used to execute an atomic sequence of data transfers,
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* each represented by a struct spi_transfer. The sequence is "atomic"
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* in the sense that no other spi_message may use that SPI bus until that
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* sequence completes. On some systems, many such sequences can execute as
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* as single programmed DMA transfer. On all systems, these messages are
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* queued, and might complete after transactions to other devices. Messages
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* sent to a given spi_device are alway executed in FIFO order.
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*
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* The code that submits an spi_message (and its spi_transfers)
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* to the lower layers is responsible for managing its memory.
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* Zero-initialize every field you don't set up explicitly, to
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* insulate against future API updates. After you submit a message
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* and its transfers, ignore them until its completion callback.
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*/
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struct spi_message {
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struct list_head transfers;
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struct spi_device *spi;
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unsigned is_dma_mapped:1;
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/* REVISIT: we might want a flag affecting the behavior of the
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* last transfer ... allowing things like "read 16 bit length L"
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* immediately followed by "read L bytes". Basically imposing
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* a specific message scheduling algorithm.
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*
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* Some controller drivers (message-at-a-time queue processing)
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* could provide that as their default scheduling algorithm. But
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* others (with multi-message pipelines) could need a flag to
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* tell them about such special cases.
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*/
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/* completion is reported through a callback */
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void (*complete)(void *context);
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void *context;
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unsigned actual_length;
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int status;
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/* for optional use by whatever driver currently owns the
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* spi_message ... between calls to spi_async and then later
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* complete(), that's the spi_master controller driver.
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*/
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struct list_head queue;
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void *state;
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};
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static inline void spi_message_init(struct spi_message *m)
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{
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memset(m, 0, sizeof *m);
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INIT_LIST_HEAD(&m->transfers);
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}
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static inline void
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spi_message_add_tail(struct spi_transfer *t, struct spi_message *m)
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{
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list_add_tail(&t->transfer_list, &m->transfers);
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}
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static inline void
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spi_transfer_del(struct spi_transfer *t)
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{
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list_del(&t->transfer_list);
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}
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/* It's fine to embed message and transaction structures in other data
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* structures so long as you don't free them while they're in use.
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*/
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static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags)
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{
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struct spi_message *m;
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m = kzalloc(sizeof(struct spi_message)
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+ ntrans * sizeof(struct spi_transfer),
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flags);
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if (m) {
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int i;
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struct spi_transfer *t = (struct spi_transfer *)(m + 1);
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INIT_LIST_HEAD(&m->transfers);
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for (i = 0; i < ntrans; i++, t++)
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spi_message_add_tail(t, m);
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}
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return m;
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}
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static inline void spi_message_free(struct spi_message *m)
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{
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kfree(m);
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}
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/**
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* spi_setup -- setup SPI mode and clock rate
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* @spi: the device whose settings are being modified
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*
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* SPI protocol drivers may need to update the transfer mode if the
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* device doesn't work with the mode 0 default. They may likewise need
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* to update clock rates or word sizes from initial values. This function
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* changes those settings, and must be called from a context that can sleep.
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* The changes take effect the next time the device is selected and data
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* is transferred to or from it.
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*/
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static inline int
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spi_setup(struct spi_device *spi)
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{
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return spi->master->setup(spi);
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}
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/**
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* spi_async -- asynchronous SPI transfer
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* @spi: device with which data will be exchanged
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* @message: describes the data transfers, including completion callback
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*
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* This call may be used in_irq and other contexts which can't sleep,
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* as well as from task contexts which can sleep.
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*
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* The completion callback is invoked in a context which can't sleep.
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* Before that invocation, the value of message->status is undefined.
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* When the callback is issued, message->status holds either zero (to
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* indicate complete success) or a negative error code. After that
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* callback returns, the driver which issued the transfer request may
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* deallocate the associated memory; it's no longer in use by any SPI
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* core or controller driver code.
|
|
*
|
|
* Note that although all messages to a spi_device are handled in
|
|
* FIFO order, messages may go to different devices in other orders.
|
|
* Some device might be higher priority, or have various "hard" access
|
|
* time requirements, for example.
|
|
*
|
|
* On detection of any fault during the transfer, processing of
|
|
* the entire message is aborted, and the device is deselected.
|
|
* Until returning from the associated message completion callback,
|
|
* no other spi_message queued to that device will be processed.
|
|
* (This rule applies equally to all the synchronous transfer calls,
|
|
* which are wrappers around this core asynchronous primitive.)
|
|
*/
|
|
static inline int
|
|
spi_async(struct spi_device *spi, struct spi_message *message)
|
|
{
|
|
message->spi = spi;
|
|
return spi->master->transfer(spi, message);
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
|
|
/* All these synchronous SPI transfer routines are utilities layered
|
|
* over the core async transfer primitive. Here, "synchronous" means
|
|
* they will sleep uninterruptibly until the async transfer completes.
|
|
*/
|
|
|
|
extern int spi_sync(struct spi_device *spi, struct spi_message *message);
|
|
|
|
/**
|
|
* spi_write - SPI synchronous write
|
|
* @spi: device to which data will be written
|
|
* @buf: data buffer
|
|
* @len: data buffer size
|
|
*
|
|
* This writes the buffer and returns zero or a negative error code.
|
|
* Callable only from contexts that can sleep.
|
|
*/
|
|
static inline int
|
|
spi_write(struct spi_device *spi, const u8 *buf, size_t len)
|
|
{
|
|
struct spi_transfer t = {
|
|
.tx_buf = buf,
|
|
.len = len,
|
|
};
|
|
struct spi_message m;
|
|
|
|
spi_message_init(&m);
|
|
spi_message_add_tail(&t, &m);
|
|
return spi_sync(spi, &m);
|
|
}
|
|
|
|
/**
|
|
* spi_read - SPI synchronous read
|
|
* @spi: device from which data will be read
|
|
* @buf: data buffer
|
|
* @len: data buffer size
|
|
*
|
|
* This writes the buffer and returns zero or a negative error code.
|
|
* Callable only from contexts that can sleep.
|
|
*/
|
|
static inline int
|
|
spi_read(struct spi_device *spi, u8 *buf, size_t len)
|
|
{
|
|
struct spi_transfer t = {
|
|
.rx_buf = buf,
|
|
.len = len,
|
|
};
|
|
struct spi_message m;
|
|
|
|
spi_message_init(&m);
|
|
spi_message_add_tail(&t, &m);
|
|
return spi_sync(spi, &m);
|
|
}
|
|
|
|
/* this copies txbuf and rxbuf data; for small transfers only! */
|
|
extern int spi_write_then_read(struct spi_device *spi,
|
|
const u8 *txbuf, unsigned n_tx,
|
|
u8 *rxbuf, unsigned n_rx);
|
|
|
|
/**
|
|
* spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
|
|
* @spi: device with which data will be exchanged
|
|
* @cmd: command to be written before data is read back
|
|
*
|
|
* This returns the (unsigned) eight bit number returned by the
|
|
* device, or else a negative error code. Callable only from
|
|
* contexts that can sleep.
|
|
*/
|
|
static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd)
|
|
{
|
|
ssize_t status;
|
|
u8 result;
|
|
|
|
status = spi_write_then_read(spi, &cmd, 1, &result, 1);
|
|
|
|
/* return negative errno or unsigned value */
|
|
return (status < 0) ? status : result;
|
|
}
|
|
|
|
/**
|
|
* spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
|
|
* @spi: device with which data will be exchanged
|
|
* @cmd: command to be written before data is read back
|
|
*
|
|
* This returns the (unsigned) sixteen bit number returned by the
|
|
* device, or else a negative error code. Callable only from
|
|
* contexts that can sleep.
|
|
*
|
|
* The number is returned in wire-order, which is at least sometimes
|
|
* big-endian.
|
|
*/
|
|
static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd)
|
|
{
|
|
ssize_t status;
|
|
u16 result;
|
|
|
|
status = spi_write_then_read(spi, &cmd, 1, (u8 *) &result, 2);
|
|
|
|
/* return negative errno or unsigned value */
|
|
return (status < 0) ? status : result;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* INTERFACE between board init code and SPI infrastructure.
|
|
*
|
|
* No SPI driver ever sees these SPI device table segments, but
|
|
* it's how the SPI core (or adapters that get hotplugged) grows
|
|
* the driver model tree.
|
|
*
|
|
* As a rule, SPI devices can't be probed. Instead, board init code
|
|
* provides a table listing the devices which are present, with enough
|
|
* information to bind and set up the device's driver. There's basic
|
|
* support for nonstatic configurations too; enough to handle adding
|
|
* parport adapters, or microcontrollers acting as USB-to-SPI bridges.
|
|
*/
|
|
|
|
/* board-specific information about each SPI device */
|
|
struct spi_board_info {
|
|
/* the device name and module name are coupled, like platform_bus;
|
|
* "modalias" is normally the driver name.
|
|
*
|
|
* platform_data goes to spi_device.dev.platform_data,
|
|
* controller_data goes to spi_device.controller_data,
|
|
* irq is copied too
|
|
*/
|
|
char modalias[KOBJ_NAME_LEN];
|
|
const void *platform_data;
|
|
void *controller_data;
|
|
int irq;
|
|
|
|
/* slower signaling on noisy or low voltage boards */
|
|
u32 max_speed_hz;
|
|
|
|
|
|
/* bus_num is board specific and matches the bus_num of some
|
|
* spi_master that will probably be registered later.
|
|
*
|
|
* chip_select reflects how this chip is wired to that master;
|
|
* it's less than num_chipselect.
|
|
*/
|
|
u16 bus_num;
|
|
u16 chip_select;
|
|
|
|
/* mode becomes spi_device.mode, and is essential for chips
|
|
* where the default of SPI_CS_HIGH = 0 is wrong.
|
|
*/
|
|
u8 mode;
|
|
|
|
/* ... may need additional spi_device chip config data here.
|
|
* avoid stuff protocol drivers can set; but include stuff
|
|
* needed to behave without being bound to a driver:
|
|
* - quirks like clock rate mattering when not selected
|
|
*/
|
|
};
|
|
|
|
#ifdef CONFIG_SPI
|
|
extern int
|
|
spi_register_board_info(struct spi_board_info const *info, unsigned n);
|
|
#else
|
|
/* board init code may ignore whether SPI is configured or not */
|
|
static inline int
|
|
spi_register_board_info(struct spi_board_info const *info, unsigned n)
|
|
{ return 0; }
|
|
#endif
|
|
|
|
|
|
/* If you're hotplugging an adapter with devices (parport, usb, etc)
|
|
* use spi_new_device() to describe each device. You can also call
|
|
* spi_unregister_device() to start making that device vanish, but
|
|
* normally that would be handled by spi_unregister_master().
|
|
*/
|
|
extern struct spi_device *
|
|
spi_new_device(struct spi_master *, struct spi_board_info *);
|
|
|
|
static inline void
|
|
spi_unregister_device(struct spi_device *spi)
|
|
{
|
|
if (spi)
|
|
device_unregister(&spi->dev);
|
|
}
|
|
|
|
#endif /* __LINUX_SPI_H */
|