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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 136 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190530000436.384967451@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
209 lines
4.3 KiB
C
209 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
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*
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* Copyright (C) 2007 ARM Limited
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*/
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#include <linux/init.h>
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#include <linux/highmem.h>
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#include <asm/cp15.h>
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#include <asm/cputype.h>
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#include <asm/cacheflush.h>
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#define CR_L2 (1 << 26)
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#define CACHE_LINE_SIZE 32
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#define CACHE_LINE_SHIFT 5
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#define CACHE_WAY_PER_SET 8
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#define CACHE_WAY_SIZE(l2ctype) (8192 << (((l2ctype) >> 8) & 0xf))
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#define CACHE_SET_SIZE(l2ctype) (CACHE_WAY_SIZE(l2ctype) >> CACHE_LINE_SHIFT)
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static inline int xsc3_l2_present(void)
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{
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unsigned long l2ctype;
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__asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
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return !!(l2ctype & 0xf8);
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}
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static inline void xsc3_l2_clean_mva(unsigned long addr)
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{
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__asm__("mcr p15, 1, %0, c7, c11, 1" : : "r" (addr));
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}
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static inline void xsc3_l2_inv_mva(unsigned long addr)
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{
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__asm__("mcr p15, 1, %0, c7, c7, 1" : : "r" (addr));
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}
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static inline void xsc3_l2_inv_all(void)
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{
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unsigned long l2ctype, set_way;
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int set, way;
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__asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
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for (set = 0; set < CACHE_SET_SIZE(l2ctype); set++) {
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for (way = 0; way < CACHE_WAY_PER_SET; way++) {
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set_way = (way << 29) | (set << 5);
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__asm__("mcr p15, 1, %0, c7, c11, 2" : : "r"(set_way));
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}
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}
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dsb();
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}
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static inline void l2_unmap_va(unsigned long va)
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{
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#ifdef CONFIG_HIGHMEM
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if (va != -1)
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kunmap_atomic((void *)va);
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#endif
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}
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static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va)
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{
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#ifdef CONFIG_HIGHMEM
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unsigned long va = prev_va & PAGE_MASK;
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unsigned long pa_offset = pa << (32 - PAGE_SHIFT);
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if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) {
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/*
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* Switching to a new page. Because cache ops are
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* using virtual addresses only, we must put a mapping
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* in place for it.
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*/
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l2_unmap_va(prev_va);
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va = (unsigned long)kmap_atomic_pfn(pa >> PAGE_SHIFT);
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}
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return va + (pa_offset >> (32 - PAGE_SHIFT));
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#else
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return __phys_to_virt(pa);
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#endif
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}
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static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long vaddr;
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if (start == 0 && end == -1ul) {
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xsc3_l2_inv_all();
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return;
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}
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vaddr = -1; /* to force the first mapping */
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/*
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* Clean and invalidate partial first cache line.
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*/
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if (start & (CACHE_LINE_SIZE - 1)) {
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vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr);
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xsc3_l2_clean_mva(vaddr);
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xsc3_l2_inv_mva(vaddr);
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start = (start | (CACHE_LINE_SIZE - 1)) + 1;
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}
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/*
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* Invalidate all full cache lines between 'start' and 'end'.
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*/
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while (start < (end & ~(CACHE_LINE_SIZE - 1))) {
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vaddr = l2_map_va(start, vaddr);
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xsc3_l2_inv_mva(vaddr);
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start += CACHE_LINE_SIZE;
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}
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/*
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* Clean and invalidate partial last cache line.
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*/
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if (start < end) {
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vaddr = l2_map_va(start, vaddr);
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xsc3_l2_clean_mva(vaddr);
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xsc3_l2_inv_mva(vaddr);
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}
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l2_unmap_va(vaddr);
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dsb();
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}
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static void xsc3_l2_clean_range(unsigned long start, unsigned long end)
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{
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unsigned long vaddr;
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vaddr = -1; /* to force the first mapping */
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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vaddr = l2_map_va(start, vaddr);
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xsc3_l2_clean_mva(vaddr);
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start += CACHE_LINE_SIZE;
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}
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l2_unmap_va(vaddr);
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dsb();
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}
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/*
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* optimize L2 flush all operation by set/way format
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*/
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static inline void xsc3_l2_flush_all(void)
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{
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unsigned long l2ctype, set_way;
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int set, way;
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__asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
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for (set = 0; set < CACHE_SET_SIZE(l2ctype); set++) {
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for (way = 0; way < CACHE_WAY_PER_SET; way++) {
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set_way = (way << 29) | (set << 5);
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__asm__("mcr p15, 1, %0, c7, c15, 2" : : "r"(set_way));
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}
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}
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dsb();
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}
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static void xsc3_l2_flush_range(unsigned long start, unsigned long end)
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{
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unsigned long vaddr;
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if (start == 0 && end == -1ul) {
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xsc3_l2_flush_all();
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return;
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}
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vaddr = -1; /* to force the first mapping */
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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vaddr = l2_map_va(start, vaddr);
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xsc3_l2_clean_mva(vaddr);
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xsc3_l2_inv_mva(vaddr);
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start += CACHE_LINE_SIZE;
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}
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l2_unmap_va(vaddr);
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dsb();
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}
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static int __init xsc3_l2_init(void)
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{
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if (!cpu_is_xsc3() || !xsc3_l2_present())
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return 0;
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if (get_cr() & CR_L2) {
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pr_info("XScale3 L2 cache enabled.\n");
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xsc3_l2_inv_all();
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outer_cache.inv_range = xsc3_l2_inv_range;
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outer_cache.clean_range = xsc3_l2_clean_range;
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outer_cache.flush_range = xsc3_l2_flush_range;
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}
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return 0;
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}
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core_initcall(xsc3_l2_init);
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