mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 16:26:46 +07:00
fb2af0020a
Pull ARM updates from Russell King:
"This contains the usual updates from other people (listed below) and
the usual random muddle of miscellaneous ARM updates which cover some
low priority bug fixes and performance improvements.
I've started to put the pull request wording into the merge commits,
which are:
- NoMMU stuff:
This includes the following series sent earlier to the list:
- nommu-fixes
- R7 Support
- MPU support
I've left out the ARCH_MULTIPLATFORM/!MMU stuff that Arnd and I
were discussing today until we've reached a conclusion/that's had
some more review.
This is rebased (and re-tested) on your devel-stable branch because
otherwise there were going to be conflicts with Uwe's V7M work now
that you've merged that. I've included the fix for limiting MPU to
CPU_V7.
- Huge page support
These changes bring both HugeTLB support and Transparent HugePage
(THP) support to ARM. Only long descriptors (LPAE) are supported
in this series.
The code has been tested on an Arndale board (Exynos 5250).
- LPAE updates
Please pull these miscellaneous LPAE fixes I've been collecting for
a while now for 3.11. They've been tested and reviewed by quite a
few people, and most of the patches are pretty trivial. -- Will Deacon.
- arch_timer cleanups
Please pull these arch_timer cleanups I've been holding onto for a
while. They're the same as my last posting, but have been rebased
to v3.10-rc3.
- mpidr linearisation (multiprocessor id register - identifies which
CPU number we are in the system)
This patch series that implements MPIDR linearization through a
simple hashing algorithm and updates current cpu_{suspend}/{resume}
code to use the newly created hash structures to retrieve context
pointers. It represents a stepping stone for the implementation of
power management code on forthcoming multi-cluster ARM systems.
It has been tested on TC2 (dual cluster A15xA7 system), iMX6q,
OMAP4 and Tegra, with processors hitting low-power states requiring
warm-boot resume through the cpu_resume code path"
* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (77 commits)
ARM: 7775/1: mm: Remove do_sect_fault from LPAE code
ARM: 7777/1: Avoid extra calls to the C compiler
ARM: 7774/1: Fix dtb dependency to use order-only prerequisites
ARM: 7770/1: remove residual ARMv2 support from decompressor
ARM: 7769/1: Cortex-A15: fix erratum 798181 implementation
ARM: 7768/1: prevent risks of out-of-bound access in ASID allocator
ARM: 7767/1: let the ASID allocator handle suspended animation
ARM: 7766/1: versatile: don't mark pen as __INIT
ARM: 7765/1: perf: Record the user-mode PC in the call chain.
ARM: 7735/2: Preserve the user r/w register TPIDRURW on context switch and fork
ARM: kernel: implement stack pointer save array through MPIDR hashing
ARM: kernel: build MPIDR hash function data structure
ARM: mpu: Ensure that MPU depends on CPU_V7
ARM: mpu: protect the vectors page with an MPU region
ARM: mpu: Allow enabling of the MPU via kconfig
ARM: 7758/1: introduce config HAS_BANDGAP
ARM: 7757/1: mm: don't flush icache in switch_mm with hardware broadcasting
ARM: 7751/1: zImage: don't overwrite ourself with a page table
ARM: 7749/1: spinlock: retry trylock operation if strex fails on free lock
ARM: 7748/1: oabi: handle faults when loading swi instruction from userspace
...
121 lines
3.3 KiB
C
121 lines
3.3 KiB
C
#ifndef __ASM_ARM_CP15_H
|
|
#define __ASM_ARM_CP15_H
|
|
|
|
#include <asm/barrier.h>
|
|
|
|
/*
|
|
* CR1 bits (CP#15 CR1)
|
|
*/
|
|
#define CR_M (1 << 0) /* MMU enable */
|
|
#define CR_A (1 << 1) /* Alignment abort enable */
|
|
#define CR_C (1 << 2) /* Dcache enable */
|
|
#define CR_W (1 << 3) /* Write buffer enable */
|
|
#define CR_P (1 << 4) /* 32-bit exception handler */
|
|
#define CR_D (1 << 5) /* 32-bit data address range */
|
|
#define CR_L (1 << 6) /* Implementation defined */
|
|
#define CR_B (1 << 7) /* Big endian */
|
|
#define CR_S (1 << 8) /* System MMU protection */
|
|
#define CR_R (1 << 9) /* ROM MMU protection */
|
|
#define CR_F (1 << 10) /* Implementation defined */
|
|
#define CR_Z (1 << 11) /* Implementation defined */
|
|
#define CR_I (1 << 12) /* Icache enable */
|
|
#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
|
|
#define CR_RR (1 << 14) /* Round Robin cache replacement */
|
|
#define CR_L4 (1 << 15) /* LDR pc can set T bit */
|
|
#define CR_DT (1 << 16)
|
|
#ifdef CONFIG_MMU
|
|
#define CR_HA (1 << 17) /* Hardware management of Access Flag */
|
|
#else
|
|
#define CR_BR (1 << 17) /* MPU Background region enable (PMSA) */
|
|
#endif
|
|
#define CR_IT (1 << 18)
|
|
#define CR_ST (1 << 19)
|
|
#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
|
|
#define CR_U (1 << 22) /* Unaligned access operation */
|
|
#define CR_XP (1 << 23) /* Extended page tables */
|
|
#define CR_VE (1 << 24) /* Vectored interrupts */
|
|
#define CR_EE (1 << 25) /* Exception (Big) Endian */
|
|
#define CR_TRE (1 << 28) /* TEX remap enable */
|
|
#define CR_AFE (1 << 29) /* Access flag enable */
|
|
#define CR_TE (1 << 30) /* Thumb exception enable */
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#if __LINUX_ARM_ARCH__ >= 4
|
|
#define vectors_high() (cr_alignment & CR_V)
|
|
#else
|
|
#define vectors_high() (0)
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_CP15
|
|
|
|
extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
|
|
extern unsigned long cr_alignment; /* defined in entry-armv.S */
|
|
|
|
static inline unsigned int get_cr(void)
|
|
{
|
|
unsigned int val;
|
|
asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
|
|
return val;
|
|
}
|
|
|
|
static inline void set_cr(unsigned int val)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
|
|
: : "r" (val) : "cc");
|
|
isb();
|
|
}
|
|
|
|
static inline unsigned int get_auxcr(void)
|
|
{
|
|
unsigned int val;
|
|
asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val));
|
|
return val;
|
|
}
|
|
|
|
static inline void set_auxcr(unsigned int val)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
|
|
: : "r" (val));
|
|
isb();
|
|
}
|
|
|
|
#ifndef CONFIG_SMP
|
|
extern void adjust_cr(unsigned long mask, unsigned long set);
|
|
#endif
|
|
|
|
#define CPACC_FULL(n) (3 << (n * 2))
|
|
#define CPACC_SVC(n) (1 << (n * 2))
|
|
#define CPACC_DISABLE(n) (0 << (n * 2))
|
|
|
|
static inline unsigned int get_copro_access(void)
|
|
{
|
|
unsigned int val;
|
|
asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
|
|
: "=r" (val) : : "cc");
|
|
return val;
|
|
}
|
|
|
|
static inline void set_copro_access(unsigned int val)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
|
|
: : "r" (val) : "cc");
|
|
isb();
|
|
}
|
|
|
|
#else /* ifdef CONFIG_CPU_CP15 */
|
|
|
|
/*
|
|
* cr_alignment and cr_no_alignment are tightly coupled to cp15 (at least in the
|
|
* minds of the developers). Yielding 0 for machines without a cp15 (and making
|
|
* it read-only) is fine for most cases and saves quite some #ifdeffery.
|
|
*/
|
|
#define cr_no_alignment UL(0)
|
|
#define cr_alignment UL(0)
|
|
|
|
#endif /* ifdef CONFIG_CPU_CP15 / else */
|
|
|
|
#endif /* ifndef __ASSEMBLY__ */
|
|
|
|
#endif
|