mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
41a1bde367
With direct submission being disabled while the reset in progress, we have a small window where we may forgo the submission of a new request and not notice its addition during execlists_reset_finish. To close this window, always schedule the submission tasklet on coming out of reset to catch any residual work. <6> [333.144082] i915: Running intel_hangcheck_live_selftests/igt_reset_engines <3> [333.296927] i915_reset_engine(rcs0:idle): failed to idle after reset <6> [333.296932] i915 0000:00:02.0: [drm] rcs0 <6> [333.296934] i915 0000:00:02.0: [drm] Hangcheck 0:a9ddf7a5 [4157 ms] <6> [333.296936] i915 0000:00:02.0: [drm] Reset count: 36048 (global 754) <6> [333.296938] i915 0000:00:02.0: [drm] Requests: <6> [333.296997] i915 0000:00:02.0: [drm] RING_START: 0x00000000 <6> [333.296999] i915 0000:00:02.0: [drm] RING_HEAD: 0x00000000 <6> [333.297001] i915 0000:00:02.0: [drm] RING_TAIL: 0x00000000 <6> [333.297003] i915 0000:00:02.0: [drm] RING_CTL: 0x00000000 <6> [333.297005] i915 0000:00:02.0: [drm] RING_MODE: 0x00000200 [idle] <6> [333.297007] i915 0000:00:02.0: [drm] RING_IMR: fffffeff <6> [333.297010] i915 0000:00:02.0: [drm] ACTHD: 0x00000000_00000000 <6> [333.297012] i915 0000:00:02.0: [drm] BBADDR: 0x00000000_00000000 <6> [333.297015] i915 0000:00:02.0: [drm] DMA_FADDR: 0x00000000_00000000 <6> [333.297017] i915 0000:00:02.0: [drm] IPEIR: 0x00000000 <6> [333.297019] i915 0000:00:02.0: [drm] IPEHR: 0x00000000 <6> [333.297021] i915 0000:00:02.0: [drm] Execlist status: 0x00000001 00000000 <6> [333.297023] i915 0000:00:02.0: [drm] Execlist CSB read 5, write 5 [mmio:7], tasklet queued? no (enabled) <6> [333.297025] i915 0000:00:02.0: [drm] ELSP[0] idle <6> [333.297027] i915 0000:00:02.0: [drm] ELSP[1] idle <6> [333.297028] i915 0000:00:02.0: [drm] HW active? 0x0 <6> [333.297044] i915 0000:00:02.0: [drm] Queue priority hint: -8186 <6> [333.297067] i915 0000:00:02.0: [drm] Q 2afac:5f2+ prio=-8186 @ 50ms: (null) <6> [333.297068] i915 0000:00:02.0: [drm] HWSP: <6> [333.297071] i915 0000:00:02.0: [drm] [0000] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 <6> [333.297073] i915 0000:00:02.0: [drm] * <6> [333.297075] i915 0000:00:02.0: [drm] [0040] 00000001 00000000 00000018 00000002 00000001 00000000 00000018 00000000 <6> [333.297077] i915 0000:00:02.0: [drm] [0060] 00000001 00000000 00008002 00000002 00000000 00000000 00000000 00000005 <6> [333.297079] i915 0000:00:02.0: [drm] [0080] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 <6> [333.297081] i915 0000:00:02.0: [drm] * <6> [333.297083] i915 0000:00:02.0: [drm] [00c0] 00000000 00000000 00000000 00000000 a9ddf7a5 00000000 00000000 00000000 <6> [333.297085] i915 0000:00:02.0: [drm] [00e0] 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 <6> [333.297087] i915 0000:00:02.0: [drm] * <6> [333.297089] i915 0000:00:02.0: [drm] Idle? no <6> [333.297090] i915_reset_engine(rcs0:idle): 3000 resets <3> [333.297092] i915/intel_hangcheck_live_selftests: igt_reset_engines failed with error -5 <3> [333.455460] i915 0000:00:02.0: Failed to idle engines, declaring wedged! ... <0> [333.491294] i915_sel-4916 1.... 333262143us : i915_reset_engine: rcs0 flags=4 <0> [333.491328] i915_sel-4916 1.... 333262143us : execlists_reset_prepare: rcs0: depth<-0 <0> [333.491362] i915_sel-4916 1.... 333262143us : intel_engine_stop_cs: rcs0 <0> [333.491396] i915_sel-4916 1d..1 333262144us : process_csb: rcs0 cs-irq head=5, tail=5 <0> [333.491424] i915_sel-4916 1.... 333262145us : intel_gpu_reset: engine_mask=1 <0> [333.491454] kworker/-214 5.... 333262184us : i915_gem_switch_to_kernel_context: awake?=yes <0> [333.491487] kworker/-214 5.... 333262192us : i915_request_add: rcs0 fence 2afac:1522 <0> [333.491520] kworker/-214 5.... 333262193us : i915_request_add: marking (null) as active <0> [333.491553] i915_sel-4916 1.... 333262199us : intel_engine_cancel_stop_cs: rcs0 <0> [333.491587] i915_sel-4916 1.... 333262199us : execlists_reset_finish: rcs0: depth->0 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190313162835.30228-1-chris@chris-wilson.co.uk
100 lines
3.0 KiB
C
100 lines
3.0 KiB
C
/*
|
|
* Copyright © 2016 Intel Corporation
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice (including the next
|
|
* paragraph) shall be included in all copies or substantial portions of the
|
|
* Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
|
* IN THE SOFTWARE.
|
|
*
|
|
*/
|
|
|
|
#ifndef __I915_GEM_H__
|
|
#define __I915_GEM_H__
|
|
|
|
#include <linux/bug.h>
|
|
#include <linux/interrupt.h>
|
|
|
|
struct drm_i915_private;
|
|
|
|
#ifdef CONFIG_DRM_I915_DEBUG_GEM
|
|
|
|
#define GEM_SHOW_DEBUG() (drm_debug & DRM_UT_DRIVER)
|
|
|
|
#define GEM_BUG_ON(condition) do { if (unlikely((condition))) { \
|
|
pr_err("%s:%d GEM_BUG_ON(%s)\n", \
|
|
__func__, __LINE__, __stringify(condition)); \
|
|
GEM_TRACE("%s:%d GEM_BUG_ON(%s)\n", \
|
|
__func__, __LINE__, __stringify(condition)); \
|
|
BUG(); \
|
|
} \
|
|
} while(0)
|
|
#define GEM_WARN_ON(expr) WARN_ON(expr)
|
|
|
|
#define GEM_DEBUG_DECL(var) var
|
|
#define GEM_DEBUG_EXEC(expr) expr
|
|
#define GEM_DEBUG_BUG_ON(expr) GEM_BUG_ON(expr)
|
|
#define GEM_DEBUG_WARN_ON(expr) GEM_WARN_ON(expr)
|
|
|
|
#else
|
|
|
|
#define GEM_SHOW_DEBUG() (0)
|
|
|
|
#define GEM_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
|
|
#define GEM_WARN_ON(expr) ({ unlikely(!!(expr)); })
|
|
|
|
#define GEM_DEBUG_DECL(var)
|
|
#define GEM_DEBUG_EXEC(expr) do { } while (0)
|
|
#define GEM_DEBUG_BUG_ON(expr)
|
|
#define GEM_DEBUG_WARN_ON(expr) ({ BUILD_BUG_ON_INVALID(expr); 0; })
|
|
#endif
|
|
|
|
#if IS_ENABLED(CONFIG_DRM_I915_TRACE_GEM)
|
|
#define GEM_TRACE(...) trace_printk(__VA_ARGS__)
|
|
#define GEM_TRACE_DUMP() ftrace_dump(DUMP_ALL)
|
|
#define GEM_TRACE_DUMP_ON(expr) \
|
|
do { if (expr) ftrace_dump(DUMP_ALL); } while (0)
|
|
#else
|
|
#define GEM_TRACE(...) do { } while (0)
|
|
#define GEM_TRACE_DUMP() do { } while (0)
|
|
#define GEM_TRACE_DUMP_ON(expr) BUILD_BUG_ON_INVALID(expr)
|
|
#endif
|
|
|
|
#define I915_NUM_ENGINES 8
|
|
|
|
#define I915_GEM_IDLE_TIMEOUT (HZ / 5)
|
|
|
|
void i915_gem_park(struct drm_i915_private *i915);
|
|
void i915_gem_unpark(struct drm_i915_private *i915);
|
|
|
|
static inline void __tasklet_disable_sync_once(struct tasklet_struct *t)
|
|
{
|
|
if (!atomic_fetch_inc(&t->count))
|
|
tasklet_unlock_wait(t);
|
|
}
|
|
|
|
static inline bool __tasklet_is_enabled(const struct tasklet_struct *t)
|
|
{
|
|
return !atomic_read(&t->count);
|
|
}
|
|
|
|
static inline bool __tasklet_enable(struct tasklet_struct *t)
|
|
{
|
|
return atomic_dec_and_test(&t->count);
|
|
}
|
|
|
|
#endif /* __I915_GEM_H__ */
|