Yong Zhi 0d95d06a7a ASoC: intel: board: sof_rt5682: Update rt1015 pll input clk freq ... In commit d696a61413 ("ASoC: rt1015: Add condition to prevent SoC providing bclk in ratio of 50 times of sample rate."), PLL input at 50fs is no longer supported, the new recommended settings at 48Khz rate are: PLL input SSP bclk ------------------------ 64fs 3.073Mhz 100fs 4.8Mhz (bclk update is reflected in topoplogy.) Signed-off-by: Yong Zhi <yong.zhi@intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Link: https://lore.kernel.org/r/20200717211337.31956-6-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>		2020-07-20 16:08:23 +01:00
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pci	ALSA: hda: fix snd_hda_codec_cleanup() documentation	2020-07-16 20:59:13 +01:00
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soc	ASoC: intel: board: sof_rt5682: Update rt1015 pll input clk freq	2020-07-20 16:08:23 +01:00
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