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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ed06efb801
There was a integer wraparound when mode_clock became too high,
and we didn't correct for the FEC overhead factor when dividing,
with the calculations breaking at HBR3.
As a result our calculated bpp was way too high, and the link width
limitation never came into effect.
Print out the resulting bpp calcululations as a sanity check, just
in case we ever have to debug it later on again.
We also used the wrong factor for FEC. While bspec mentions 2.4%,
all the calculations use 1/0.972261, and the same ratio should be
applied to data M/N as well, so use it there when FEC is enabled.
This fixes the FIFO underrun we are seeing with FEC enabled.
Changes since v2:
- Handle fec_enable in intel_link_compute_m_n, so only data M/N is adjusted. (Ville)
- Fix initial hardware readout for FEC. (Ville)
Changes since v3:
- Remove bogus fec_to_mode_clock. (Ville)
Changes since v4:
- Use the correct register for icl. (Ville)
- Split hw readout to a separate patch.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Fixes: d9218c8f6c ("drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC")
Cc: <stable@vger.kernel.org> # v5.0+
Cc: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190925082110.17439-1-maarten.lankhorst@linux.intel.com
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
121 lines
4.6 KiB
C
121 lines
4.6 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DP_H__
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#define __INTEL_DP_H__
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#include <linux/types.h>
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#include <drm/i915_drm.h>
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#include "i915_reg.h"
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enum pipe;
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enum port;
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struct drm_connector_state;
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struct drm_encoder;
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struct drm_i915_private;
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struct drm_modeset_acquire_ctx;
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struct intel_connector;
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struct intel_crtc_state;
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struct intel_digital_port;
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struct intel_dp;
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struct intel_encoder;
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struct link_config_limits {
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int min_clock, max_clock;
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int min_lane_count, max_lane_count;
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int min_bpp, max_bpp;
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};
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void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
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struct intel_crtc_state *pipe_config,
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struct link_config_limits *limits);
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bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
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bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
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i915_reg_t dp_reg, enum port port,
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enum pipe *pipe);
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bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
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enum port port);
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bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
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struct intel_connector *intel_connector);
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void intel_dp_set_link_params(struct intel_dp *intel_dp,
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int link_rate, u8 lane_count,
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bool link_mst);
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int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
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int link_rate, u8 lane_count);
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int intel_dp_retrain_link(struct intel_encoder *encoder,
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struct drm_modeset_acquire_ctx *ctx);
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void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
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void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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bool enable);
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void intel_dp_encoder_reset(struct drm_encoder *encoder);
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void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
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void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
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int intel_dp_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state);
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bool intel_dp_is_edp(struct intel_dp *intel_dp);
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bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
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enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
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bool long_hpd);
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void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
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void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
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void intel_edp_panel_on(struct intel_dp *intel_dp);
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void intel_edp_panel_off(struct intel_dp *intel_dp);
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void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
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void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
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int intel_dp_max_link_rate(struct intel_dp *intel_dp);
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int intel_dp_max_lane_count(struct intel_dp *intel_dp);
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int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
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void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
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u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
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void intel_edp_drrs_enable(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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void intel_edp_drrs_disable(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
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unsigned int frontbuffer_bits);
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void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
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unsigned int frontbuffer_bits);
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void
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intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
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u8 dp_train_pat);
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void
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intel_dp_set_signal_levels(struct intel_dp *intel_dp);
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void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
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u8
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intel_dp_voltage_max(struct intel_dp *intel_dp);
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u8
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intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
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void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
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u8 *link_bw, u8 *rate_select);
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bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
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bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
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bool
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intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status);
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bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
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bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
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int intel_dp_link_required(int pixel_clock, int bpp);
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int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
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bool intel_digital_port_connected(struct intel_encoder *encoder);
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static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
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{
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return ~((1 << lane_count) - 1) & 0xf;
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}
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u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
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#endif /* __INTEL_DP_H__ */
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