Chris Brandt f59de56335 clk: renesas: mstp: ensure register writes complete ... When there is no status bit, it is possible for the clock enable/disable operation to have not completed by the time the driver code resumes execution. This is due to the fact that write operations are sometimes queued and delayed internally. Doing a read ensures the write operations has completed. Fixes: b6face404f ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi") Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2017-02-16 10:36:05 -08:00
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clk-div6.c
clk-div6.h
clk-emev2.c
clk-mstp.c
clk-r8a73a4.c
clk-r8a7740.c
clk-r8a7778.c
clk-r8a7779.c
clk-rcar-gen2.c
clk-rz.c
clk-sh73a0.c
Kconfig
Makefile
r8a7743-cpg-mssr.c
r8a7745-cpg-mssr.c
r8a7795-cpg-mssr.c
r8a7796-cpg-mssr.c
rcar-gen2-cpg.c
rcar-gen2-cpg.h
rcar-gen3-cpg.c
rcar-gen3-cpg.h
renesas-cpg-mssr.c
renesas-cpg-mssr.h