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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* OMAP2+ MPU WD_TIMER-specific code
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*
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* Copyright (C) 2012 Texas Instruments, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/platform_data/omap-wd-timer.h>
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#include "omap_hwmod.h"
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#include "omap_device.h"
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#include "wd_timer.h"
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#include "common.h"
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#include "prm.h"
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#include "soc.h"
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/*
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* In order to avoid any assumptions from bootloader regarding WDT
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* settings, WDT module is reset during init. This enables the watchdog
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* timer. Hence it is required to disable the watchdog after the WDT reset
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* during init. Otherwise the system would reboot as per the default
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* watchdog timer registers settings.
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*/
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#define OMAP_WDT_WPS 0x34
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#define OMAP_WDT_SPR 0x48
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int omap2_wd_timer_disable(struct omap_hwmod *oh)
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{
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void __iomem *base;
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if (!oh) {
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pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
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return -EINVAL;
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}
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base = omap_hwmod_get_mpu_rt_va(oh);
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if (!base) {
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pr_err("%s: Could not get the base address for %s\n",
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oh->name, __func__);
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return -EINVAL;
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}
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/* sequence required to disable watchdog */
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writel_relaxed(0xAAAA, base + OMAP_WDT_SPR);
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while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
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cpu_relax();
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writel_relaxed(0x5555, base + OMAP_WDT_SPR);
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while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
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cpu_relax();
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return 0;
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}
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/**
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* omap2_wdtimer_reset - reset and disable the WDTIMER IP block
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* @oh: struct omap_hwmod *
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*
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* After the WDTIMER IP blocks are reset on OMAP2/3, we must also take
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* care to execute the special watchdog disable sequence. This is
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* because the watchdog is re-armed upon OCP softreset. (On OMAP4,
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* this behavior was apparently changed and the watchdog is no longer
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* re-armed after an OCP soft-reset.) Returns -ETIMEDOUT if the reset
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* did not complete, or 0 upon success.
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*
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* XXX Most of this code should be moved to the omap_hwmod.c layer
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* during a normal merge window. omap_hwmod_softreset() should be
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* renamed to omap_hwmod_set_ocp_softreset(), and omap_hwmod_softreset()
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* should call the hwmod _ocp_softreset() code.
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*/
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int omap2_wd_timer_reset(struct omap_hwmod *oh)
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{
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int c = 0;
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/* Write to the SOFTRESET bit */
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omap_hwmod_softreset(oh);
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/* Poll on RESETDONE bit */
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omap_test_timeout((omap_hwmod_read(oh,
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oh->class->sysc->syss_offs)
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& SYSS_RESETDONE_MASK),
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MAX_MODULE_SOFTRESET_WAIT, c);
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if (oh->class->sysc->srst_udelay)
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udelay(oh->class->sysc->srst_udelay);
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if (c == MAX_MODULE_SOFTRESET_WAIT)
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pr_warn("%s: %s: softreset failed (waited %d usec)\n",
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__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
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else
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pr_debug("%s: %s: softreset in %d usec\n", __func__,
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oh->name, c);
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return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT :
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omap2_wd_timer_disable(oh);
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}
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