mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 03:26:40 +07:00
f8f235e5bb
Sandybridge GTT has new cache control bits in PTE, which controls graphics page cache in LLC or LLC/MLC, so we need to extend the mask function to respect the new bits. And set cache control to always LLC only by default on Gen6. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
21 lines
427 B
C
21 lines
427 B
C
/*
|
|
* Common Intel AGPGART and GTT definitions.
|
|
*/
|
|
#ifndef _INTEL_GTT_H
|
|
#define _INTEL_GTT_H
|
|
|
|
#include <linux/agp_backend.h>
|
|
|
|
/* This is for Intel only GTT controls.
|
|
*
|
|
* Sandybridge: AGP_USER_CACHED_MEMORY default to LLC only
|
|
*/
|
|
|
|
#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
|
|
#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
|
|
|
|
/* flag for GFDT type */
|
|
#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
|
|
|
|
#endif
|