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Intel WiFi devices 3945 and 4965 now have their own driver in the folder drivers/net/wireless/iwlegacy Add support to build these drivers independently of the driver for AGN devices. Selecting the 3945 builds iwl3945.ko and iwl_legacy.ko, and selecting the 4965 builds iwl4965.ko and iwl_legacy.ko. iwl-legacy.ko contains code shared between both devices. The 3945 is an ABG/BG device, with no support for 802.11n. The 4965 is a 2x3 ABGN device. Signed-off-by: Meenakshi Venkataraman <meenakshi.venkataraman@intel.com> Acked-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
188 lines
7.2 KiB
C
188 lines
7.2 KiB
C
/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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#ifndef __iwl_3945_fh_h__
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#define __iwl_3945_fh_h__
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/************************************/
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/* iwl3945 Flow Handler Definitions */
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/************************************/
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/**
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* This I/O area is directly read/writable by driver (e.g. Linux uses writel())
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* Addresses are offsets from device's PCI hardware base address.
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*/
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#define FH39_MEM_LOWER_BOUND (0x0800)
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#define FH39_MEM_UPPER_BOUND (0x1000)
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#define FH39_CBCC_TABLE (FH39_MEM_LOWER_BOUND + 0x140)
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#define FH39_TFDB_TABLE (FH39_MEM_LOWER_BOUND + 0x180)
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#define FH39_RCSR_TABLE (FH39_MEM_LOWER_BOUND + 0x400)
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#define FH39_RSSR_TABLE (FH39_MEM_LOWER_BOUND + 0x4c0)
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#define FH39_TCSR_TABLE (FH39_MEM_LOWER_BOUND + 0x500)
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#define FH39_TSSR_TABLE (FH39_MEM_LOWER_BOUND + 0x680)
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/* TFDB (Transmit Frame Buffer Descriptor) */
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#define FH39_TFDB(_ch, buf) (FH39_TFDB_TABLE + \
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((_ch) * 2 + (buf)) * 0x28)
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#define FH39_TFDB_CHNL_BUF_CTRL_REG(_ch) (FH39_TFDB_TABLE + 0x50 * (_ch))
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/* CBCC channel is [0,2] */
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#define FH39_CBCC(_ch) (FH39_CBCC_TABLE + (_ch) * 0x8)
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#define FH39_CBCC_CTRL(_ch) (FH39_CBCC(_ch) + 0x00)
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#define FH39_CBCC_BASE(_ch) (FH39_CBCC(_ch) + 0x04)
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/* RCSR channel is [0,2] */
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#define FH39_RCSR(_ch) (FH39_RCSR_TABLE + (_ch) * 0x40)
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#define FH39_RCSR_CONFIG(_ch) (FH39_RCSR(_ch) + 0x00)
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#define FH39_RCSR_RBD_BASE(_ch) (FH39_RCSR(_ch) + 0x04)
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#define FH39_RCSR_WPTR(_ch) (FH39_RCSR(_ch) + 0x20)
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#define FH39_RCSR_RPTR_ADDR(_ch) (FH39_RCSR(_ch) + 0x24)
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#define FH39_RSCSR_CHNL0_WPTR (FH39_RCSR_WPTR(0))
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/* RSSR */
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#define FH39_RSSR_CTRL (FH39_RSSR_TABLE + 0x000)
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#define FH39_RSSR_STATUS (FH39_RSSR_TABLE + 0x004)
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/* TCSR */
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#define FH39_TCSR(_ch) (FH39_TCSR_TABLE + (_ch) * 0x20)
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#define FH39_TCSR_CONFIG(_ch) (FH39_TCSR(_ch) + 0x00)
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#define FH39_TCSR_CREDIT(_ch) (FH39_TCSR(_ch) + 0x04)
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#define FH39_TCSR_BUFF_STTS(_ch) (FH39_TCSR(_ch) + 0x08)
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/* TSSR */
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#define FH39_TSSR_CBB_BASE (FH39_TSSR_TABLE + 0x000)
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#define FH39_TSSR_MSG_CONFIG (FH39_TSSR_TABLE + 0x008)
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#define FH39_TSSR_TX_STATUS (FH39_TSSR_TABLE + 0x010)
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/* DBM */
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#define FH39_SRVC_CHNL (6)
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#define FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
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#define FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
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#define FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
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#define FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
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#define FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
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#define FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
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#define FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
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#define FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
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#define FH39_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
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#define FH39_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
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#define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) (BIT(_ch) << 24)
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#define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch) (BIT(_ch) << 16)
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#define FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_ch) \
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(FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) | \
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FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch))
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#define FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
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struct iwl3945_tfd_tb {
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__le32 addr;
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__le32 len;
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} __packed;
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struct iwl3945_tfd {
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__le32 control_flags;
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struct iwl3945_tfd_tb tbs[4];
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u8 __pad[28];
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} __packed;
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#endif /* __iwl_3945_fh_h__ */
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