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The display architecture on Tegra186 and Tegra194 requires that there be some valid clock on all domains before accessing any display register. A further requirement is that in addition to the host1x, hub, disp and dsc clocks, all the head clocks (pclk0-2 on Tegra186 or pclk0-3 on Tegra194) must also be enabled. Implement this logic within the display hub driver to ensure the clocks are always enabled at the right time. Signed-off-by: Thierry Reding <treding@nvidia.com> |
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| .. | ||
| drm | ||
| host1x | ||
| ipu-v3 | ||
| vga | ||
| Makefile | ||