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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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435 lines
19 KiB
C
435 lines
19 KiB
C
/*
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* linux/include/asm-arm/io.h
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*
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* Copyright (C) 1996-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Modifications:
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* 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
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* constant addresses and variable addresses.
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* 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
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* specific IO header files.
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* 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
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* 04-Apr-1999 PJB Added check_signature.
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* 12-Dec-1999 RMK More cleanups
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* 18-Jun-2000 RMK Removed virt_to_* and friends definitions
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*/
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#ifndef __ASM_ARM_IO_H
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#define __ASM_ARM_IO_H
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <asm/memory.h>
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#include <asm/hardware.h>
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/*
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* Generic IO read/write. These perform native-endian accesses. Note
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* that some architectures will want to re-define __raw_{read,write}w.
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*/
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extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
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extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
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extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
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extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
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extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
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extern void __raw_readsl(unsigned int addr, void *data, int longlen);
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#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
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#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
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#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
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#define __raw_readb(a) (*(volatile unsigned char *)(a))
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#define __raw_readw(a) (*(volatile unsigned short *)(a))
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#define __raw_readl(a) (*(volatile unsigned int *)(a))
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/*
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* Bad read/write accesses...
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*/
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extern void __readwrite_bug(const char *fn);
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/*
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* Now, pick up the machine-defined IO definitions
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*/
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#define IO_SPACE_LIMIT 0xffffffff
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/*
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* GCC is totally crap at loading/storing data. We try to persuade it
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* to do the right thing by using these whereever possible instead of
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* the above.
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*/
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#define __arch_base_getb(b,o) \
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({ \
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unsigned int v, r = (b); \
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__asm__ __volatile__( \
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"ldrb %0, [%1, %2]" \
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: "=r" (v) \
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: "r" (r), "Ir" (o)); \
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v; \
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})
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#define __arch_base_getl(b,o) \
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({ \
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unsigned int v, r = (b); \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2]" \
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: "=r" (v) \
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: "r" (r), "Ir" (o)); \
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v; \
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})
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#define __arch_base_putb(v,b,o) \
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({ \
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unsigned int r = (b); \
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__asm__ __volatile__( \
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"strb %0, [%1, %2]" \
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: \
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: "r" (v), "r" (r), "Ir" (o)); \
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})
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#define __arch_base_putl(v,b,o) \
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({ \
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unsigned int r = (b); \
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__asm__ __volatile__( \
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"str %0, [%1, %2]" \
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: \
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: "r" (v), "r" (r), "Ir" (o)); \
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})
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/*
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* We use two different types of addressing - PC style addresses, and ARM
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* addresses. PC style accesses the PC hardware with the normal PC IO
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* addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+
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* and are translated to the start of IO. Note that all addresses are
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* shifted left!
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*/
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#define __PORT_PCIO(x) (!((x) & 0x80000000))
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/*
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* Dynamic IO functions - let the compiler
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* optimize the expressions
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*/
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static inline void __outb (unsigned int value, unsigned int port)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"tst %2, #0x80000000\n\t"
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"mov %0, %4\n\t"
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"addeq %0, %0, %3\n\t"
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"strb %1, [%0, %2, lsl #2] @ outb"
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: "=&r" (temp)
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: "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
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: "cc");
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}
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static inline void __outw (unsigned int value, unsigned int port)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"tst %2, #0x80000000\n\t"
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"mov %0, %4\n\t"
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"addeq %0, %0, %3\n\t"
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"str %1, [%0, %2, lsl #2] @ outw"
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: "=&r" (temp)
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: "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
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: "cc");
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}
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static inline void __outl (unsigned int value, unsigned int port)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"tst %2, #0x80000000\n\t"
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"mov %0, %4\n\t"
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"addeq %0, %0, %3\n\t"
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"str %1, [%0, %2, lsl #2] @ outl"
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: "=&r" (temp)
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: "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
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: "cc");
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}
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#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
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static inline unsigned sz __in##fnsuffix (unsigned int port) \
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{ \
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unsigned long temp, value; \
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__asm__ __volatile__( \
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"tst %2, #0x80000000\n\t" \
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"mov %0, %4\n\t" \
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"addeq %0, %0, %3\n\t" \
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"ldr" instr " %1, [%0, %2, lsl #2] @ in" #fnsuffix \
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: "=&r" (temp), "=r" (value) \
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: "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \
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: "cc"); \
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return (unsigned sz)value; \
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}
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static inline unsigned int __ioaddr (unsigned int port) \
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{ \
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if (__PORT_PCIO(port)) \
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return (unsigned int)(PCIO_BASE + (port << 2)); \
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else \
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return (unsigned int)(IO_BASE + (port << 2)); \
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}
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#define DECLARE_IO(sz,fnsuffix,instr) \
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DECLARE_DYN_IN(sz,fnsuffix,instr)
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DECLARE_IO(char,b,"b")
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DECLARE_IO(short,w,"")
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DECLARE_IO(int,l,"")
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#undef DECLARE_IO
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#undef DECLARE_DYN_IN
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/*
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* Constant address IO functions
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*
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* These have to be macros for the 'J' constraint to work -
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* +/-4096 immediate operand.
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*/
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#define __outbc(value,port) \
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({ \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"strb %0, [%1, %2] @ outbc" \
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: : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"strb %0, [%1, %2] @ outbc" \
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: : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \
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})
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#define __inbc(port) \
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({ \
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unsigned char result; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"ldrb %0, [%1, %2] @ inbc" \
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: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"ldrb %0, [%1, %2] @ inbc" \
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: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
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result; \
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})
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#define __outwc(value,port) \
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({ \
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unsigned long v = value; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"str %0, [%1, %2] @ outwc" \
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: : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"str %0, [%1, %2] @ outwc" \
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: : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2)); \
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})
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#define __inwc(port) \
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({ \
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unsigned short result; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2] @ inwc" \
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: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2] @ inwc" \
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: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
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result & 0xffff; \
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})
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#define __outlc(value,port) \
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({ \
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unsigned long v = value; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"str %0, [%1, %2] @ outlc" \
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: : "r" (v), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"str %0, [%1, %2] @ outlc" \
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: : "r" (v), "r" (IO_BASE), "r" ((port) << 2)); \
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})
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#define __inlc(port) \
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({ \
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unsigned long result; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2] @ inlc" \
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: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2] @ inlc" \
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: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
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result; \
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})
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#define __ioaddrc(port) \
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({ \
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unsigned long addr; \
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if (__PORT_PCIO((port))) \
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addr = PCIO_BASE + ((port) << 2); \
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else \
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addr = IO_BASE + ((port) << 2); \
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addr; \
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})
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#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
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#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
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#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
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#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
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#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
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#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
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#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p))
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/* JMA 18.02.03 added sb,sl from arm/io.h, changing io to ioaddr */
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#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
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#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
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#define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l)
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#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
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#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
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#define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l)
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#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
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#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
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#define readb(c) (__readwrite_bug("readb"),0)
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#define readw(c) (__readwrite_bug("readw"),0)
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#define readl(c) (__readwrite_bug("readl"),0)
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#define readb_relaxed(addr) readb(addr)
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#define readw_relaxed(addr) readw(addr)
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#define readl_relaxed(addr) readl(addr)
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#define writeb(v,c) __readwrite_bug("writeb")
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#define writew(v,c) __readwrite_bug("writew")
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#define writel(v,c) __readwrite_bug("writel")
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#define readsw(p,d,l) (__readwrite_bug("readsw"),0)
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#define readsl(p,d,l) (__readwrite_bug("readsl"),0)
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#define writesw(p,d,l) __readwrite_bug("writesw")
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#define writesl(p,d,l) __readwrite_bug("writesl")
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#define mmiowb()
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/* the following macro is depreciated */
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#define ioaddr(port) __ioaddr((port))
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/*
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* No ioremap support here.
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*/
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#define __arch_ioremap(c,s,f,a) ((void *)(c))
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#define __arch_iounmap(c) do { } while (0)
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#if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \
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defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl)
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#warning machine class uses old __arch_putw or __arch_getw
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#endif
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/*
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* IO port access primitives
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* -------------------------
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*
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* The ARM doesn't have special IO access instructions; all IO is memory
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* mapped. Note that these are defined to perform little endian accesses
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* only. Their primary purpose is to access PCI and ISA peripherals.
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*
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* Note that for a big endian machine, this implies that the following
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* big endian mode connectivity is in place, as described by numerious
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* ARM documents:
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*
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* PCI: D0-D7 D8-D15 D16-D23 D24-D31
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* ARM: D24-D31 D16-D23 D8-D15 D0-D7
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*
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* The machine specific io.h include defines __io to translate an "IO"
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* address to a memory address.
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*
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* Note that we prevent GCC re-ordering or caching values in expressions
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* by introducing sequence points into the in*() definitions. Note that
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* __raw_* do not guarantee this behaviour.
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*/
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/*
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#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
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#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
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#define insb(p,d,l) __raw_readsb(__io(p),d,l)
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#define insw(p,d,l) __raw_readsw(__io(p),d,l)
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*/
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#define outb_p(val,port) outb((val),(port))
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#define outw_p(val,port) outw((val),(port))
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#define inb_p(port) inb((port))
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#define inw_p(port) inw((port))
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#define inl_p(port) inl((port))
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#define outsb_p(port,from,len) outsb(port,from,len)
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#define outsw_p(port,from,len) outsw(port,from,len)
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#define insb_p(port,to,len) insb(port,to,len)
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#define insw_p(port,to,len) insw(port,to,len)
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/*
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* String version of IO memory access ops:
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*/
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extern void _memcpy_fromio(void *, unsigned long, size_t);
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extern void _memcpy_toio(unsigned long, const void *, size_t);
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extern void _memset_io(unsigned long, int, size_t);
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/*
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* ioremap and friends.
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*
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* ioremap takes a PCI memory address, as specified in
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* Documentation/IO-mapping.txt.
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*/
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extern void * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
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extern void __iounmap(void *addr);
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#ifndef __arch_ioremap
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#define ioremap(cookie,size) __ioremap(cookie,size,0,1)
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#define ioremap_nocache(cookie,size) __ioremap(cookie,size,0,1)
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#define iounmap(cookie) __iounmap(cookie)
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#else
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#define ioremap(cookie,size) __arch_ioremap((cookie),(size),0,1)
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#define ioremap_nocache(cookie,size) __arch_ioremap((cookie),(size),0,1)
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#define iounmap(cookie) __arch_iounmap(cookie)
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#endif
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/*
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* DMA-consistent mapping functions. These allocate/free a region of
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* uncached, unwrite-buffered mapped memory space for use with DMA
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* devices. This is the "generic" version. The PCI specific version
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* is in pci.h
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*/
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extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
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extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
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extern void consistent_sync(void *vaddr, size_t size, int rw);
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/*
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* can the hardware map this into one segment or not, given no other
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* constraints.
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*/
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#define BIOVEC_MERGEABLE(vec1, vec2) \
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((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif /* __KERNEL__ */
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#endif /* __ASM_ARM_IO_H */
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