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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 03:06:43 +07:00
a2ffcf87f5
In general Renesas hardware is not documented to the extent where the relationship between IP blocks on different SoCs can be assumed although they may appear to operate the same way. Furthermore the documentation typically does not specify a version for individual IP blocks. For these reasons a convention of using the SoC name in place of a version and providing SoC-specific compat strings has been adopted. Although not universally liked this convention is used in the bindings for a number of drivers for Renesas hardware. The purpose of this patch is to make use of the SoC-specific CMT compat string for the r8a7740 48-bit CMT clock source. Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
513 lines
14 KiB
Plaintext
513 lines
14 KiB
Plaintext
/*
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* Device Tree Source for the r8a7740 SoC
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/include/ "skeleton.dtsi"
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#include <dt-bindings/clock/r8a7740-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "renesas,r8a7740";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0x0>;
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clock-frequency = <800000000>;
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};
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};
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gic: interrupt-controller@c2800000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xc2800000 0x1000>,
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<0xc2000000 0x1000>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
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};
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cmt1: timer@e6138000 {
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compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
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reg = <0xe6138000 0x170>;
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interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
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clock-names = "fck";
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renesas,channels-mask = <0x3f>;
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status = "disabled";
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};
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/* irqpin0: IRQ0 - IRQ7 */
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irqpin0: irqpin@e6900000 {
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compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900000 4>,
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<0xe6900010 4>,
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<0xe6900020 1>,
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<0xe6900040 1>,
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<0xe6900060 1>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* irqpin1: IRQ8 - IRQ15 */
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irqpin1: irqpin@e6900004 {
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compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900004 4>,
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<0xe6900014 4>,
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<0xe6900024 1>,
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<0xe6900044 1>,
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<0xe6900064 1>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* irqpin2: IRQ16 - IRQ23 */
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irqpin2: irqpin@e6900008 {
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compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900008 4>,
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<0xe6900018 4>,
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<0xe6900028 1>,
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<0xe6900048 1>,
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<0xe6900068 1>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* irqpin3: IRQ24 - IRQ31 */
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irqpin3: irqpin@e690000c {
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compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe690000c 4>,
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<0xe690001c 4>,
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<0xe690002c 1>,
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<0xe690004c 1>,
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<0xe690006c 1>;
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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};
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ether: ethernet@e9a00000 {
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compatible = "renesas,gether-r8a7740";
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reg = <0xe9a00000 0x800>,
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<0xe9a01800 0x800>;
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interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
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phy-mode = "mii";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c0: i2c@fff20000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
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reg = <0xfff20000 0x425>;
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interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH
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0 202 IRQ_TYPE_LEVEL_HIGH
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0 203 IRQ_TYPE_LEVEL_HIGH
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0 204 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
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status = "disabled";
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};
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i2c1: i2c@e6c20000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
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reg = <0xe6c20000 0x425>;
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interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH
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0 71 IRQ_TYPE_LEVEL_HIGH
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0 72 IRQ_TYPE_LEVEL_HIGH
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0 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
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status = "disabled";
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};
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scifa0: serial@e6c40000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c40000 0x100>;
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interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa1: serial@e6c50000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c50000 0x100>;
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interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa2: serial@e6c60000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c60000 0x100>;
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interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa3: serial@e6c70000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c70000 0x100>;
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interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa4: serial@e6c80000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6c80000 0x100>;
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interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa5: serial@e6cb0000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6cb0000 0x100>;
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interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa6: serial@e6cc0000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6cc0000 0x100>;
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifa7: serial@e6cd0000 {
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compatible = "renesas,scifa-r8a7740", "renesas,scifa";
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reg = <0xe6cd0000 0x100>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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scifb8: serial@e6c30000 {
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compatible = "renesas,scifb-r8a7740", "renesas,scifb";
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reg = <0xe6c30000 0x100>;
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
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clock-names = "sci_ick";
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status = "disabled";
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};
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pfc: pfc@e6050000 {
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compatible = "renesas,pfc-r8a7740";
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reg = <0xe6050000 0x8000>,
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<0xe605800c 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts-extended =
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<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
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<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
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<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
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<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
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<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
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<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
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<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
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<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
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};
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tpu: pwm@e6600000 {
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compatible = "renesas,tpu-r8a7740", "renesas,tpu";
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reg = <0xe6600000 0x100>;
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clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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mmcif0: mmc@e6bd0000 {
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compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
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reg = <0xe6bd0000 0x100>;
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interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
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0 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_MMC>;
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status = "disabled";
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};
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sdhi0: sd@e6850000 {
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compatible = "renesas,sdhi-r8a7740";
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reg = <0xe6850000 0x100>;
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interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
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0 118 IRQ_TYPE_LEVEL_HIGH
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0 119 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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sdhi1: sd@e6860000 {
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compatible = "renesas,sdhi-r8a7740";
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reg = <0xe6860000 0x100>;
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interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
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0 122 IRQ_TYPE_LEVEL_HIGH
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0 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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sdhi2: sd@e6870000 {
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compatible = "renesas,sdhi-r8a7740";
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reg = <0xe6870000 0x100>;
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interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
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0 126 IRQ_TYPE_LEVEL_HIGH
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0 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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};
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sh_fsi2: sound@fe1f0000 {
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#sound-dai-cells = <1>;
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compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
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reg = <0xfe1f0000 0x400>;
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interrupts = <0 9 0x4>;
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clocks = <&mstp3_clks R8A7740_CLK_FSI>;
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status = "disabled";
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* External root clock */
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extalr_clk: extalr_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "extalr";
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};
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extal1_clk: extal1_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "extal1";
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};
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extal2_clk: extal2_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "extal2";
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};
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dv_clk: dv_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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clock-output-names = "dv";
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};
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fsiack_clk: fsiack_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "fsiack";
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};
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fsibck_clk: fsibck_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "fsibck";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7740-cpg-clocks";
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reg = <0xe6150000 0x10000>;
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clocks = <&extal1_clk>, <&extalr_clk>;
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#clock-cells = <1>;
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clock-output-names = "system", "pllc0", "pllc1",
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"pllc2", "r",
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"usb24s",
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"i", "zg", "b", "m1", "hp",
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"hpp", "usbp", "s", "zb", "m3",
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"cp";
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};
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/* Variable factor clocks (DIV6) */
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sub_clk: sub_clk@e6150080 {
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compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
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reg = <0xe6150080 4>;
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clocks = <&pllc1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sub";
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};
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/* Fixed factor clocks */
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pllc1_div2_clk: pllc1_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "pllc1_div2";
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};
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extal1_div2_clk: extal1_div2_clk {
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compatible = "fixed-factor-clock";
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clocks = <&extal1_clk>;
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#clock-cells = <0>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "extal1_div2";
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};
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/* Gate clocks */
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subck_clks: subck_clks@e6150080 {
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compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150080 4>;
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clocks = <&sub_clk>, <&sub_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
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>;
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clock-output-names =
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"subck", "subck2";
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};
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mstp1_clks: mstp1_clks@e6150134 {
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compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150134 4>, <0xe6150038 4>;
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clocks = <&cpg_clocks R8A7740_CLK_S>,
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<&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
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<&cpg_clocks R8A7740_CLK_B>,
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<&sub_clk>, <&sub_clk>,
|
|
<&cpg_clocks R8A7740_CLK_B>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
|
|
R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
|
|
R8A7740_CLK_LCDC0
|
|
>;
|
|
clock-output-names =
|
|
"ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
|
|
"tmu1", "lcdc0";
|
|
};
|
|
mstp2_clks: mstp2_clks@e6150138 {
|
|
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0xe6150138 4>, <0xe6150040 4>;
|
|
clocks = <&sub_clk>, <&sub_clk>,
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
<&sub_clk>, <&sub_clk>, <&sub_clk>,
|
|
<&sub_clk>, <&sub_clk>, <&sub_clk>,
|
|
<&sub_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7
|
|
R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
|
|
R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
|
|
R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
|
|
R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
|
|
R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
|
|
R8A7740_CLK_SCIFA4
|
|
>;
|
|
clock-output-names =
|
|
"scifa6", "scifa7", "dmac1", "dmac2", "dmac3",
|
|
"usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
|
|
"scifa2", "scifa3", "scifa4";
|
|
};
|
|
mstp3_clks: mstp3_clks@e615013c {
|
|
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0xe615013c 4>, <0xe6150048 4>;
|
|
clocks = <&cpg_clocks R8A7740_CLK_R>,
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
<&sub_clk>,
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
<&cpg_clocks R8A7740_CLK_HP>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
|
|
R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
|
|
R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
|
|
>;
|
|
clock-output-names =
|
|
"cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
|
|
"mmc", "gether", "tpu0";
|
|
};
|
|
mstp4_clks: mstp4_clks@e6150140 {
|
|
compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0xe6150140 4>, <0xe615004c 4>;
|
|
clocks = <&cpg_clocks R8A7740_CLK_HP>,
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
<&cpg_clocks R8A7740_CLK_HP>,
|
|
<&cpg_clocks R8A7740_CLK_HP>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7740_CLK_USBH R8A7740_CLK_SDHI2
|
|
R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
|
|
>;
|
|
clock-output-names =
|
|
"usbhost", "sdhi2", "usbfunc", "usphy";
|
|
};
|
|
};
|
|
};
|