Shaokun Zhang 9a83c84c3a drivers: base: cacheinfo: Add variable to record max cache line size ... Add coherency_max_size variable to record the maximum cache line size for different cache levels. If it is available, we will synchronize it as cache line size, otherwise we will use CTR_EL0.CWG reporting in cache_line_size() for arm64. Cc: "Rafael J. Wysocki" <rafael@kernel.org> Cc: Jeremy Linton <jeremy.linton@arm.com> Cc: Will Deacon <will.deacon@arm.com> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>		2019-06-04 13:42:54 +01:00
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firmware_loader
power	More power management updates for 5.2-rc1	2019-05-15 08:46:44 -07:00
regmap
test
arch_topology.c
attribute_container.c
base.h
bus.c
cacheinfo.c	drivers: base: cacheinfo: Add variable to record max cache line size	2019-06-04 13:42:54 +01:00
class.c
component.c
container.c
core.c
cpu.c	Merge branch 'x86-mds-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2019-05-14 07:57:29 -07:00
dd.c
devcon.c
devcoredump.c
devres.c
devtmpfs.c
driver.c
firmware.c
hypervisor.c
init.c
isa.c
Kconfig	Driver core/kobject patches for 5.2-rc1	2019-05-07 13:01:40 -07:00
Makefile
map.c
memory.c	mm/memory_hotplug: make unregister_memory_section() never fail	2019-05-14 09:47:49 -07:00
module.c
node.c
pinctrl.c
platform-msi.c
platform.c
property.c
soc.c
swnode.c
syscore.c
topology.c
transport_class.c