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The Keystone PCIe controller is based on v3.65 version of the Designware h/w. Main differences are: 1. No ATU support 2. Legacy and MSI IRQ functions are implemented in application register space 3. MSI interrupts are multiplexed over 8 IRQ lines to the Host side. All of the application register space handing code is organized into pci-keystone-dw.c and the functions are called from pci-keystone.c to implement PCI controller driver. Also add necessary DT documentation and update the MAINTAINERS file for the driver. [bhelgaas: spelling and whitespace fixes] Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> CC: Russell King <linux@arm.linux.org.uk> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Mohit Kumar <mohit.kumar@st.com> CC: Pratyush Anand <pratyush.anand@st.com> CC: Jingoo Han <jg1.han@samsung.com> CC: Richard Zhu <r65037@freescale.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Marek Vasut <marex@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org> CC: Randy Dunlap <rdunlap@infradead.org> CC: Grant Likely <grant.likely@linaro.org>
69 lines
2.4 KiB
Plaintext
69 lines
2.4 KiB
Plaintext
TI Keystone PCIe interface
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Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
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It shares common functions with PCIe Designware core driver and inherit
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common properties defined in
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Documentation/devicetree/bindings/pci/designware-pci.txt
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Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
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for the details of Designware DT bindings. Additional properties are
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described here as well as properties that are not applicable.
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Required Properties:-
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compatibility: "ti,keystone-pcie"
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reg: index 1 is the base address and length of DW application registers.
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index 2 is the base address and length of PCI mode configuration
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register.
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index 3 is the base address and length of PCI device ID register.
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pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
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interrupt-cells: should be set to 1
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interrupt-parent: Parent interrupt controller phandle
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interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
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Example:
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pcie_msi_intc: msi-interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
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};
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pcie_intc: Interrupt controller device node for Legacy IRQ chip
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interrupt-cells: should be set to 1
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interrupt-parent: Parent interrupt controller phandle
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interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines
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Example:
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pcie_intc: legacy-interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
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};
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Optional properties:-
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phys: phandle to Generic Keystone SerDes phy for PCI
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phy-names: name of the Generic Keystine SerDes phy for PCI
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- If boot loader already does PCI link establishment, then phys and
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phy-names shouldn't be present.
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Designware DT Properties not applicable for Keystone PCI
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1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
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Note for PCI driver usage
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=========================
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Driver requires pci=pcie_bus_perf in the bootargs for proper functioning.
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