linux_dsm_epyc7002/Documentation/devicetree/bindings/pci/pci-keystone.txt
Murali Karicheri 0c4ffcfe1f PCI: keystone: Add TI Keystone PCIe driver
The Keystone PCIe controller is based on v3.65 version of the Designware
h/w.  Main differences are:

    1. No ATU support
    2. Legacy and MSI IRQ functions are implemented in application register
       space
    3. MSI interrupts are multiplexed over 8 IRQ lines to the Host side.

All of the application register space handing code is organized into
pci-keystone-dw.c and the functions are called from pci-keystone.c to
implement PCI controller driver.  Also add necessary DT documentation and
update the MAINTAINERS file for the driver.

[bhelgaas: spelling and whitespace fixes]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Mohit Kumar <mohit.kumar@st.com>
CC: Pratyush Anand <pratyush.anand@st.com>
CC: Jingoo Han <jg1.han@samsung.com>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
2014-09-04 14:58:21 -06:00

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TI Keystone PCIe interface
Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
It shares common functions with PCIe Designware core driver and inherit
common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt
Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
for the details of Designware DT bindings. Additional properties are
described here as well as properties that are not applicable.
Required Properties:-
compatibility: "ti,keystone-pcie"
reg: index 1 is the base address and length of DW application registers.
index 2 is the base address and length of PCI mode configuration
register.
index 3 is the base address and length of PCI device ID register.
pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
interrupt-cells: should be set to 1
interrupt-parent: Parent interrupt controller phandle
interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
Example:
pcie_msi_intc: msi-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
};
pcie_intc: Interrupt controller device node for Legacy IRQ chip
interrupt-cells: should be set to 1
interrupt-parent: Parent interrupt controller phandle
interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines
Example:
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
};
Optional properties:-
phys: phandle to Generic Keystone SerDes phy for PCI
phy-names: name of the Generic Keystine SerDes phy for PCI
- If boot loader already does PCI link establishment, then phys and
phy-names shouldn't be present.
Designware DT Properties not applicable for Keystone PCI
1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
Note for PCI driver usage
=========================
Driver requires pci=pcie_bus_perf in the bootargs for proper functioning.