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eac1e731b5
This is the framework for using XIVE in a PowerVM guest. The support is very similar to the native one in a much simpler form. Each source is associated with an Event State Buffer (ESB). This is a two bit state machine which is used to trigger events. The bits are named "P" (pending) and "Q" (queued) and can be controlled by MMIO. The Guest OS registers event (or notifications) queues on which the HW will post event data for a target to notify. Instead of OPAL calls, a set of Hypervisors call are used to configure the interrupt sources and the event/notification queues of the guest: - H_INT_GET_SOURCE_INFO used to obtain the address of the MMIO page of the Event State Buffer (PQ bits) entry associated with the source. - H_INT_SET_SOURCE_CONFIG assigns a source to a "target". - H_INT_GET_SOURCE_CONFIG determines to which "target" and "priority" is assigned to a source - H_INT_GET_QUEUE_INFO returns the address of the notification management page associated with the specified "target" and "priority". - H_INT_SET_QUEUE_CONFIG sets or resets the event queue for a given "target" and "priority". It is also used to set the notification config associated with the queue, only unconditional notification for the moment. Reset is performed with a queue size of 0 and queueing is disabled in that case. - H_INT_GET_QUEUE_CONFIG returns the queue settings for a given "target" and "priority". - H_INT_RESET resets all of the partition's interrupt exploitation structures to their initial state, losing all configuration set via the hcalls H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG. - H_INT_SYNC issue a synchronisation on a source to make sure sure all notifications have reached their queue. As for XICS, the XIVE interface for the guest is described in the device tree under the "interrupt-controller" node. A couple of new properties are specific to XIVE : - "reg" contains the base address and size of the thread interrupt managnement areas (TIMA), also called rings, for the User level and for the Guest OS level. Only the Guest OS level is taken into account today. - "ibm,xive-eq-sizes" the size of the event queues. One cell per size supported, contains log2 of size, in ascending order. - "ibm,xive-lisn-ranges" the interrupt numbers ranges assigned to the guest. These are allocated using a simple bitmap. and also : - "/ibm,plat-res-int-priorities" contains a list of priorities that the hypervisor has reserved for its own use. Tested with a QEMU XIVE model for pseries and with the Power hypervisor. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
293 lines
6.8 KiB
C
293 lines
6.8 KiB
C
/*
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* SMP support for pSeries machines.
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*
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* Dave Engebretsen, Peter Bergner, and
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* Mike Corrigan {engebret|bergner|mikec}@us.ibm.com
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*
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* Plus various changes from other IBM teams...
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/cache.h>
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/cpu.h>
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#include <asm/ptrace.h>
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#include <linux/atomic.h>
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#include <asm/irq.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/smp.h>
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#include <asm/paca.h>
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#include <asm/machdep.h>
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#include <asm/cputable.h>
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#include <asm/firmware.h>
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#include <asm/rtas.h>
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#include <asm/vdso_datapage.h>
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#include <asm/cputhreads.h>
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#include <asm/xics.h>
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#include <asm/xive.h>
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#include <asm/dbell.h>
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#include <asm/plpar_wrappers.h>
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#include <asm/code-patching.h>
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#include "pseries.h"
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#include "offline_states.h"
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/*
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* The Primary thread of each non-boot processor was started from the OF client
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* interface by prom_hold_cpus and is spinning on secondary_hold_spinloop.
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*/
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static cpumask_var_t of_spin_mask;
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/* Query where a cpu is now. Return codes #defined in plpar_wrappers.h */
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int smp_query_cpu_stopped(unsigned int pcpu)
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{
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int cpu_status, status;
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int qcss_tok = rtas_token("query-cpu-stopped-state");
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if (qcss_tok == RTAS_UNKNOWN_SERVICE) {
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printk_once(KERN_INFO
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"Firmware doesn't support query-cpu-stopped-state\n");
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return QCSS_HARDWARE_ERROR;
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}
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status = rtas_call(qcss_tok, 1, 2, &cpu_status, pcpu);
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if (status != 0) {
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printk(KERN_ERR
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"RTAS query-cpu-stopped-state failed: %i\n", status);
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return status;
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}
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return cpu_status;
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}
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/**
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* smp_startup_cpu() - start the given cpu
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*
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* At boot time, there is nothing to do for primary threads which were
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* started from Open Firmware. For anything else, call RTAS with the
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* appropriate start location.
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*
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* Returns:
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* 0 - failure
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* 1 - success
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*/
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static inline int smp_startup_cpu(unsigned int lcpu)
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{
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int status;
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unsigned long start_here =
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__pa(ppc_function_entry(generic_secondary_smp_init));
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unsigned int pcpu;
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int start_cpu;
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if (cpumask_test_cpu(lcpu, of_spin_mask))
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/* Already started by OF and sitting in spin loop */
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return 1;
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pcpu = get_hard_smp_processor_id(lcpu);
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/* Check to see if the CPU out of FW already for kexec */
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if (smp_query_cpu_stopped(pcpu) == QCSS_NOT_STOPPED){
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cpumask_set_cpu(lcpu, of_spin_mask);
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return 1;
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}
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/* Fixup atomic count: it exited inside IRQ handler. */
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task_thread_info(paca[lcpu].__current)->preempt_count = 0;
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#ifdef CONFIG_HOTPLUG_CPU
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if (get_cpu_current_state(lcpu) == CPU_STATE_INACTIVE)
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goto out;
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#endif
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/*
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* If the RTAS start-cpu token does not exist then presume the
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* cpu is already spinning.
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*/
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start_cpu = rtas_token("start-cpu");
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if (start_cpu == RTAS_UNKNOWN_SERVICE)
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return 1;
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status = rtas_call(start_cpu, 3, 1, NULL, pcpu, start_here, pcpu);
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if (status != 0) {
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printk(KERN_ERR "start-cpu failed: %i\n", status);
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return 0;
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}
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#ifdef CONFIG_HOTPLUG_CPU
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out:
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#endif
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return 1;
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}
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static void smp_setup_cpu(int cpu)
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{
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if (xive_enabled())
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xive_smp_setup_cpu();
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else if (cpu != boot_cpuid)
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xics_setup_cpu();
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if (firmware_has_feature(FW_FEATURE_SPLPAR))
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vpa_init(cpu);
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cpumask_clear_cpu(cpu, of_spin_mask);
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#ifdef CONFIG_HOTPLUG_CPU
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set_cpu_current_state(cpu, CPU_STATE_ONLINE);
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set_default_offline_state(cpu);
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#endif
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}
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static int smp_pSeries_kick_cpu(int nr)
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{
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if (nr < 0 || nr >= nr_cpu_ids)
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return -EINVAL;
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if (!smp_startup_cpu(nr))
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return -ENOENT;
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/*
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* The processor is currently spinning, waiting for the
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* cpu_start field to become non-zero After we set cpu_start,
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* the processor will continue on to secondary_start
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*/
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paca[nr].cpu_start = 1;
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#ifdef CONFIG_HOTPLUG_CPU
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set_preferred_offline_state(nr, CPU_STATE_ONLINE);
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if (get_cpu_current_state(nr) == CPU_STATE_INACTIVE) {
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long rc;
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unsigned long hcpuid;
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hcpuid = get_hard_smp_processor_id(nr);
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rc = plpar_hcall_norets(H_PROD, hcpuid);
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if (rc != H_SUCCESS)
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printk(KERN_ERR "Error: Prod to wake up processor %d "
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"Ret= %ld\n", nr, rc);
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}
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#endif
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return 0;
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}
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static int pseries_smp_prepare_cpu(int cpu)
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{
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if (xive_enabled())
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return xive_smp_prepare_cpu(cpu);
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return 0;
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}
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static void smp_pseries_cause_ipi(int cpu)
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{
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/* POWER9 should not use this handler */
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if (doorbell_try_core_ipi(cpu))
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return;
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icp_ops->cause_ipi(cpu);
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}
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static int pseries_cause_nmi_ipi(int cpu)
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{
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int hwcpu;
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if (cpu == NMI_IPI_ALL_OTHERS) {
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hwcpu = H_SIGNAL_SYS_RESET_ALL_OTHERS;
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} else {
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if (cpu < 0) {
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WARN_ONCE(true, "incorrect cpu parameter %d", cpu);
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return 0;
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}
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hwcpu = get_hard_smp_processor_id(cpu);
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}
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if (plapr_signal_sys_reset(hwcpu) == H_SUCCESS)
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return 1;
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return 0;
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}
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static __init void pSeries_smp_probe_xics(void)
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{
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xics_smp_probe();
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if (cpu_has_feature(CPU_FTR_DBELL))
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smp_ops->cause_ipi = smp_pseries_cause_ipi;
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else
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smp_ops->cause_ipi = icp_ops->cause_ipi;
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}
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static __init void pSeries_smp_probe(void)
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{
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if (xive_enabled())
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/*
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* Don't use P9 doorbells when XIVE is enabled. IPIs
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* using MMIOs should be faster
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*/
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xive_smp_probe();
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else
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pSeries_smp_probe_xics();
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}
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static struct smp_ops_t pseries_smp_ops = {
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.message_pass = NULL, /* Use smp_muxed_ipi_message_pass */
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.cause_ipi = NULL, /* Filled at runtime by pSeries_smp_probe() */
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.cause_nmi_ipi = pseries_cause_nmi_ipi,
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.probe = pSeries_smp_probe,
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.prepare_cpu = pseries_smp_prepare_cpu,
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.kick_cpu = smp_pSeries_kick_cpu,
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.setup_cpu = smp_setup_cpu,
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.cpu_bootable = smp_generic_cpu_bootable,
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};
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/* This is called very early */
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void __init smp_init_pseries(void)
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{
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int i;
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pr_debug(" -> smp_init_pSeries()\n");
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smp_ops = &pseries_smp_ops;
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alloc_bootmem_cpumask_var(&of_spin_mask);
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/*
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* Mark threads which are still spinning in hold loops
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*
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* We know prom_init will not have started them if RTAS supports
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* query-cpu-stopped-state.
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*/
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if (rtas_token("query-cpu-stopped-state") == RTAS_UNKNOWN_SERVICE) {
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if (cpu_has_feature(CPU_FTR_SMT)) {
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for_each_present_cpu(i) {
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if (cpu_thread_in_core(i) == 0)
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cpumask_set_cpu(i, of_spin_mask);
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}
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} else
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cpumask_copy(of_spin_mask, cpu_present_mask);
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cpumask_clear_cpu(boot_cpuid, of_spin_mask);
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}
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/* Non-lpar has additional take/give timebase */
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if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) {
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smp_ops->give_timebase = rtas_give_timebase;
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smp_ops->take_timebase = rtas_take_timebase;
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}
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pr_debug(" <- smp_init_pSeries()\n");
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}
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